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參數(shù)資料
| 型號： | TLC1549MJG |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL |
| 中文描述： | 10位模擬數(shù)字轉(zhuǎn)換器與串行控制 |
| 文件頁數(shù)： | 11/15頁 |
| 文件大?。?/td> | 238K |
| 代理商： | TLC1549MJG |
TLC1549C, TLC1549I, TLC1549M
10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS059C – DECEMBER 1992 – REVISED MARCH 1995
11
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Sample Cycle B
A/D
Conversion
Interval
(
≤
21
μ
s)
Initialize
Initialize
MSB
LSB
Previous Conversion Data
B9
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Hi-Z State
1
2
3
4
5
6
7
8
9
10
1
I/O
CLOCK
DATA
OUT
CS
(see Note A)
Figure 6. Timing for 10-Clock Transfer Using CS
Sample Cycle B
A/D Conversion
Interval
(
≤
21
μ
s)
Initialize
MSB
LSB
Previous Conversion Data
B9
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Low Level
1
2
3
4
5
6
7
8
9
10
1
I/O
CLOCK
DATA
OUT
CS
Initialize
(see Note A)
Must Be High on Power Up
See Note C
Figure 7. Timing for 10-Clock Transfer Not Using CS
Sample Cycle B
A/D
Conversion
Interval
(
≤
21
μ
s)
Initialize
MSB
LSB
Previous Conversion Data
B9
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
1
2
3
4
5
6
7
8
9
10
1
I/O
CLOCK
DATA
OUT
CS
Initialize
Low
Level
11
16
(see Note A)
Figure 8. Timing for 11- to 16-Clock Transfer Using CS (Serial Transfer Completed Within 21
μ
s)
NOTES: A. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system
clock after CS
↓
before responding to the I/O CLOCK. No attempt should be made to clock out the data until the minimum CS setup
time has elapsed.
B. A low-to-high transition of CS disables I/O CLOCK within a maximum of a setup time plus two falling edges of the internal system
clock.
C. The first I/O CLOCK must occur after the end of the previous conversion.
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