參數(shù)資料
型號(hào): TLC1514IDG4
廠商: TEXAS INSTRUMENTS INC
元件分類: ADC
英文描述: 4-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO16
封裝: GREEN, PLASTIC, SOIC-16
文件頁(yè)數(shù): 27/37頁(yè)
文件大?。?/td> 572K
代理商: TLC1514IDG4
TLC1514, TLC1518
5-V, 10-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER,
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN
SLAS252 – DECEMBER 1999
33
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
simplified analog input analysis
Using the equivalent circuit in Figure 39, the time required to charge the analog input capacitance from 0 to VS
within 1/2 LSB can be derived as follows.
The capacitance charging voltage is given by:
Vc
+ Vs 1–EXP
–tc
Rt
Ci
Where
Rt = Rs + Zi
tc = Cycle time
(1)
The input impedance Zi is 0.5 k
at 5 V. The final voltage to 1/2 LSB is given by:
VC (1 2 LSB)
+ VS–
VS
2048
(2)
Equating equation 1 to equation 2 and solving for cycle time tc gives:
Vs–
VS
2048
+ Vs 1–EXP
–tc
Rt
Ci
(3)
and time to change to 1/2 LSB (minimum sampling time) is:
tch (1 2 LSB)
+ Rt
Ci
In(2048)
Where
In(2048) = 7.625
Therefore, with the values given, the time for the analog input signal to settle is:
tch (1 2 LSB)
+ (Rs ) 0.5 kW)
Ci
In(2048)
(4)
This time must be less than the converter sample time shown in the timing diagrams. This is 12
× SCLKs (if the
sampling mode is short normal sampling mode).
tch (1 2 LSB)
v 12
1
f (SCLK)
(5)
Therefore the maximum SCLK frequency is:
max f (SCLK)
+
12
tch 1 2 LSB
+
12
[In(2048)
Rt
Ci]
(6)
相關(guān)PDF資料
PDF描述
TLC1540CN 12-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDIP20
TLC1540CFN 12-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PQCC20
TLC1540CDW 12-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20
TLC1541CDWR 11-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20
TLC1541CFN 11-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PQCC20
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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