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參數(shù)資料
| 型號： | TLC0820AIN |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, PDIP20 |
| 封裝： | ROHS COMPLIANT, PLASTIC, DIP-20 |
| 文件頁數(shù)： | 12/15頁 |
| 文件大?。?/td> | 345K |
| 代理商： | TLC0820AIN |
TLC0820AC, TLC0820AI
Advanced LinCMOS
HIGH-SPEED 8-BIT ANALOG-TO-DIGITAL
CONVERTERS USING MODIFIED FLASH TECHNIQUES
SLAS064A – SEPTEMBER 1986 – REVISED JUNE 1994
2–6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
operating characteristics, VCC = 5 V, Vref+ = 5 V, Vref– = 0, tr = tf = 20 ns, TA = 25C (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
kSVS
Supply-voltage sensitivity
VCC = 5 V ± 5%,
TA = MIN to MAX
±1/16
±1/4
LSB
Total unadjusted error
MODE at 0 V,
TA = MIN to MAX
1
LSB
tconv(R) Conversion time, read mode
MODE at 0 V,
See Figure 1
1.6
2.5
s
ta(R)
Access time, RD
↓ to data valid
MODE at 0 V,
See Figure 1
tconv(R)
+20
tconv(R)
+50
ns
t (R1)
Access time RD
↓ to data valid
MODE at 5 V,
td(WR) <td(i )
CL = 15 pF
190
280
ns
ta(R1)
Access time, RD
↓ to data valid
td(WR) < td(int),
See Figure 2
CL = 100 pF
210
320
ns
t (R2)
Access time RD
↓ to data valid
MODE at 5 V,
td(WR) >td(i )
CL = 15 pF
70
120
ns
ta(R2)
Access time, RD
↓ to data valid
td(WR) > td(int),
See Figure 3
CL = 100 pF
90
150
ns
ta(INT)
Access time, INT
↓ to data valid
MODE at 5 V,
See Figure 4
20
50
ns
tdis
Disable time RD
↑ to data valid
RL = 1 k,
CL = 10 pF,
70
95
ns
tdis
Disable time, RD
↑ to data valid
See Figures 1, 2, 3, and 5
70
95
ns
td(int)
Delay time WR/RDY
↑ to INT↓
MODE at 5 V,
CL = 50 pF,
800
1300
ns
td(int)
Delay time, WR/RDY
↑ to INT↓
See Figures 2, 3, and 4
800
1300
ns
td(NC)
Delay time, to next conversion
See Figures 1, 2, 3, and 4
500
ns
td(WR)
Delay time, WR/RDY
↑ to RD↓ in
write-read mode
See Figure 2
0.4
s
td(RDY)
Delay time CS
↓ to WR/RDY↓
MODE at 0 V,
CL = 50 pF,
50
100
ns
td(RDY)
Delay time, CS
↓ to WR/RDY↓
See Figure 1
50
100
ns
td(RIH)
Delay time, RD
↑ to INT↑
CL = 50 pF,
See Figures 1, 2, and 3
125
225
ns
td(RIL)
Delay time RD
↓ to INT↓
MODE at 5 V,
td(WR) < td(int),
200
290
ns
td(RIL)
Delay time, RD
↓ to INT↓
See Figure 2
200
290
ns
td(WIH)
Delay time WR/RDY
↑ to INT↑
MODE at 5 V,
CL = 50 pF,
175
270
ns
td(WIH)
Delay time, WR/RDY
↑ to INT↑
See Figure 4
175
270
ns
Slew-rate tracking
0.1
V/
s
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
Total unadjusted error includes offset, full-scale, and linearity errors.
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