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參數(shù)資料
| 型號(hào)： | TL811 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | STB/PVR Controller IC |
| 中文描述： | 機(jī)頂盒/殘余尿控制芯片 |
| 文件頁(yè)數(shù)： | 2/2頁(yè) |
| 文件大?。?/td> | 199K |
| 代理商： | TL811 |
Copyright 2000. TeraLogic, Inc. All rights reserved worldwide. TeraLogic and the TeraLogic logo are registered trademarks of TeraLogic, Inc. Janus is a
trademark of TeraLogic, Inc. All other trademarks are properties of their respective owners and are acknowledged.
11/00 - 5K
TeraLogic, Inc.
1240
Villa Street Mountain View
CA 94041
tel
650.526.2000
fax
650.526.2006
www.teralogic.tv
i
c
APPLICATIONS
￥
Set-Top Boxes
￥
Digital TV
￥
Personal Video Recorders
SUPPORTING TERALOGIC PRODUCTS
￥
TL85x Decoder ICs
￥
Cougar Development Platform
PROGRAMMABLE TRANSPORT
INPUT/DEMULTIPLEXER
￥
Two dedicated and one bi-directional
transport input ports
￥
One dedicated and one bi-directional
transport output ports
￥
Glueless interface to IEEE 1394 devices
￥
Two ATSC/DVB/ARIB/DIRECTV
compliant demux
￥
Glueless interface to most front-end ICs
￥
Maximum input bit rate of 80 Mbits/sec
supported on each port
￥
Ability to transfer multiple SD streams to
the TeraLogic DTV Decoder for SD PIP
applications
IDE ULTRA DMA INTERFACE
￥
Supports one IDE connector for up to 2
IDE drives
￥
Ultra DMA specifications allows 66
MByte transfer rate
SDRAM INTERFACE
￥
32-bit wide SDRAM interface
￥
Supports 16/64/128-Mbit SDRAM
devices
PCI BUS INTERFACE
￥
32-bit PCI 2.1 compliant interface
￥
50 MHz or 33 MHz bus clock
￥
PCI Master/Slave/Arbiter capability
supported
￥
Supports burst transfers for efficient data
movement
PERIPHERALS
￥
Two ISO-7816 smart card interfaces
￥
Four Asynchronous UART
￥
Two
I
2
C compatible master and slave
ports
￥
Three 32-bit timers/counters
￥
NRSS-A/NRSS-B support
￥
User-configurable general purpose I/Os
TECHNOLOGY
￥
See grid below for packaging
￥
2.5 V core, 3.3 V 1/0, 0.25
μ
CMOS
￥
352 Ball BGA
DESCRAMBLERS
￥
DVB, DIRECTV DES-ECB, MPEG DES,
Triple DES-CBC, Multi-2 descrambling
supported
￥
Simultaneous descrambling of two
streams supported
￥
All three transport input ports can access
the descramblers
￥
Bypass mode of transport streams supported
CPU INTERFACE
￥
Glueless interface to MIPS CPUs such as
QED RM5231, NEC V
R
5432
￥
32-bit wide multiplexed address/data
supported
￥
Write and Read posting buffers between
CPU and external resources (PCI, memory
bus and local bus).
LOCAL BUS
￥
Generic bus interface (16-bit data and
24-bit address bus)
￥
6 Pre-decoded, programmable chip selects
￥
Can be configured to be fixed 8-bit only,
or 8- and 16-bit width device support
TL811
STB/PVR
Controller IC
PCI Bus
TeraLogic
DTV Decoder
HD Video
Transport Out
Other Devices if required
Analog HD Out
Audio 5.1 out
SD Video Out
SD Video Capture
FLASH
EPROM
required
CPU
SDRAM
PCI BUS
Memory
Controller
TL811
Local Bus
Controller
T/S in
1
Transport In & Out
Local Bus
Transport In
Transport In
Descrambler
2
Descrambler
1
T/S in
3
T/S in 2
1
2
De
De
PVR I/O
IDE
DTV I/O
SmartCards
GPIO
UART
IDE
I
2
C
2 SmartCards
GPIO
UART
T/S Out
POD
DTV Tuner
DTV Tuner
1394
/DVCR
TL85x
CPU Interface
(SysAD Bus)
TL811 SYSTEM DIAGRAM
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