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參數資料
| 型號： | TL441N |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 運動控制電子 |
| 英文描述： | LOGARITHMIC AMPLIFIER |
| 中文描述： | 對數放大器 |
| 文件頁數： | 1/14頁 |
| 文件大?。?/td> | 233K |
| 代理商： | TL441N |
TL441AM
LOGARITHMIC AMPLIFIER
SLFS038 – JUNE 1976 – REVISED FEBRUARY 1989
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Excellent Dynamic Range
Wide Bandwidth
Built-In Temperature Compensation
Log Linearity (30 dB Sections) . . . 1 dB Typ
Wide Input Voltage Range
description
This monolithic amplifier circuit contains four
30-dB logarithmic stages. Gain in each stage is
such that the output of each stage is proportional
to the logarithm of the input voltage over the 30-dB
input voltage range. Each half of the circuit
contains two of these 30-dB stages summed
together in one differential output that is
proportional to the sum of the logarithms of the
input voltages of the two stages. The four stages
may be interconnected to obtain a theoretical
input voltage range of 120-dB. In practice, this
permits the input voltage range to be typically
greater than 80-dB with log linearity of
±
0.5-dB
(see application data). Bandwidth is from dc to
40 MHz.
This circuit is useful in military weapons systems,
broadband radar, and infrared reconnaissance
systems. It serves for data compression and
analog compensation. This logarithmic amplifier
is used in log IF circuitry as well as video and log
amplifiers. The TL441AM is characterized for
operation over the full military temperature range
of – 55
°
C to 125
°
C.
Copyright
1989, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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8
16
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C
A2
V
CC –
C
A2
′
A1
Y
Y
A2
V
CC +
NC
C
B2
C
B2
′
GND
B1
Z
Z
B2
J PACKAGE
(TOP VIEW)
3
2
1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
C
B2
′
GND
NC
B1
Z
C
A2
′
A1
NC
Y
Y
FK PACKAGE
(TOP VIEW)
C
C
N
B
Z
N
C
A
V
N
NC — No internal connection
A
B
C
–15 dB
–15 dB
Log
Log
Log
Log
Σ
Y (Z)
Y (Z)
A1
(B1)
CA2
(CB2)
CA2
′
(CB2
′
)
Y
∝
log A1 + log A2; Z
∝
log B1 + log B2
where: A1, A2, B1, and B2 are in dBV, 0 dBV = 1 V.
CA2, CA2
′
, CB2, and CB2
′
are detector compensation inputs.
A2
(B2)
functional block diagram (one half)
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