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參數(shù)資料
| 型號(hào)： | TL16C554I |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | ASYNCHRONOUS COMMUNICATIONS ELEMENT |
| 中文描述： | 異步通信元 |
| 文件頁(yè)數(shù)： | 8/33頁(yè) |
| 文件大小： | 478K |
| 代理商： | TL16C554I |
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TL16C554, TL16C554I
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS165D – JANUARY 1994 – REVISED JULY 1998
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
transmitter switching characteristics over recommended ranges of operating free-air temperature
and supply voltage (see Figures 6, 7, and 8)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
td5
Delay time, INTx
↓
to TXx
↓
at start
8
24
RCLK
cycles
td6
Delay time, TXx
↓
at start to INTx
↑
See Note 5
8
8
RCLK
cycles
td7
Delay time, IOW high or low (WR THR) to INTx
↑
See Note 5
16
32
RCLK
cycles
td8
Delay time, TXx
↓
at start to TXRDY
↓
CL = 100 pF
8
RCLK
cycles
tpd1
tpd2
tpd3
NOTE 5: If the transmitter interrupt delay is active, this delay is lengthened by one character time minus the last stop bit time.
Propagation delay time, IOW (WR THR)
↓
to INTx
↓
CL = 100 pF
CL = 100 pF
CL = 100 pF
35
ns
Propagation delay time, IOR (RD IIR)
↑
to INTx
↓
30
ns
Propagation delay time, IOW (WR THR)
↑
to TXRDY
↑
50
ns
receiver switching characteristics over recommended ranges of operating free-air temperature
and supply voltage (see Figures 9 through 13)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
td9
Delay time, stop bit to INTx
↑
or stop bit to RXRDY
↓
or read RBR to set interrupt
See Note 6
1
RCLK
cycle
tpd4
Propagation delay time, Read RBR/LSR to INTx
↓
/LSR interrupt
↓
CL = 100 pF,
See Note 7
40
ns
tpd5
NOTES:
Propagation delay time, IOR RCLK
↓
to RXRDY
↑
See Note 7
30
ns
6. The receiver data available indicator, the overrun error indicator, the trigger level interrupts, and the active RXRDY indicator are
delayed three RCLK (internal receiver timing clock) cycles in the FIFO mode (FCR0 = 1). After the first byte has been received, status
indicators (PE, FE, BI) are delayed three RCLK cycles. These indicators are updated immediately for any further bytes received after
IOR goes active for a read from the RBR register. There are eight RCLK cycle delays for trigger change level interrupts.
7. RCLK is an internal signal derived from divisor latch LSB (DLL) and divisor latch MSB (DLM) divisor latches.
modem control switching characteristics over recommended ranges of operating free-air
temperature and supply voltage, C
L
= 100 pF (see Figure 14)
PARAMETER
MIN
MAX
UNIT
tpd6
tpd7
tpd8
tpd9
Propagation delay time, IOW (WR MCR)
↑
to RTSx, DTRx
↑
50
ns
Propagation delay time, modem input CTSx, DSRx, and DCDx
↓↑
to INTx
↑
30
ns
Propagation delay time, IOR (RD MSR)
↑
to interrupt
↓
35
ns
Propagation delay time, RIx
↑
to INTx
↑
30
ns
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TL16C554IFN | 功能描述:UART 接口集成電路 Quad UART with 16-Byte FIFOs RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| TL16C554IFNG4 | 功能描述:UART 接口集成電路 Quad UART w/16-Byte FIFOs RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| TL16C554IFNR | 功能描述:UART 接口集成電路 Quad UART with 16-Byte FIFOs RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| TL16C554IFNRG4 | 功能描述:UART 接口集成電路 Quad UART w/16-Byte FIFOs RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| TL16C554IPN | 功能描述:UART 接口集成電路 Qd UART w/16b FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
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