參數(shù)資料
型號： TL16C550CIN
廠商： Texas Instruments, Inc.
英文描述： ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH AUTOFLOW CONTROL
中文描述： 異步通信與自動流速調(diào)節(jié)控制單元
文件頁數(shù)： 5/35頁
文件大?。?/td> 499K
代理商： TL16C550CIN
TL16C550B, TL16C550BI
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136B – JANUARY 1994 – REVISED AUGUST 1996
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
NO.
N
NAME
NO.
FN
NO.
PT
I/O
DESCRIPTION
A0
A1
A2
28
27
26
31
30
29
28
27
26
I
Register select. A0–A2 are used during read and write operations to select the ACE register to read
from or write to. Refer to Table 1 for register addresses, and refer to the address strobe (ADS) signal
description.
ADS
25
28
24
I
Address strobe. When ADS is active (low), the register select signals (A0, A1, and A2) and chip select
signals (CS0, CS1, CS2) drive the internal select logic directly; when high, the register select and chip
select signals are held in the state they are in when the low-to-high transition of ADS occurs.
Baud out. BAUDOUT is a 16
×
clock signal for the transmitter section of the ACE. The clock rate is
established by the reference oscillator frequency divided by a divisor specified by the baud generator
divisor latches. BAUDOUT can also be used for the receiver section by tying this output to RCLK.
BAUDOUT
15
17
12
O
CS0
CS1
CS2
12
13
14
14
15
16
9
10
11
I
Chip select. When CS0 = high, CS1 = high, and CS2 = low, these three inputs select the ACE. When
any of these inputs are inactive, the ACE remains inactive. Refer to the ADS signal description.
CTS
36
40
38
I
Clear to send. CTS is a modem status signal. Its condition can be checked by reading bit 4 (CTS) of
the modem status register. Bit 0 (
CTS) of the modem status register indicates that this signal has
changed states since the last read from the modem status register. If the modem status interrupt is
enabled when CTS changes state, an interrupt is generated.
D0
D1
D2
D3
D4
D5
D6
D7
1
2
3
4
5
6
7
8
2
3
4
5
6
7
8
9
43
44
45
46
47
2
3
4
I/O
Data bus. Eight data lines with 3-state outputs provide a bidirectional path for data, control, and status
information between the ACE and the CPU.
DCD
38
42
40
I
Data carrier detect. DCD is a modem status signal. Its condition can be checked by reading bit 7 (DCD)
of the modem status register. Bit 3 (
DCD) of the modem status register indicates that this signal has
changed states since the last read from the modem status register. If the modem status interrupt is
enabled when DCD changes state, an interrupt is generated.
DDIS
23
26
22
O
Driver disable. This output is active (high) when the CPU is not reading data. When active, this output
can disable an external transceiver.
DSR
37
41
39
I
Data set ready. DSR is a modem status signal. Its condition can be checked by reading bit 5 (DSR) of
the modem status register. Bit 1 (
DSR) of the modem status register indicates this signal has changed
states since the last read from the modem status register. If the modem status interrupt is enabled when
DSR changes state, an interrupt is generated.
DTR
33
37
33
O
Data terminal ready. When active (low), DTR informs a modem or data set that the ACE is ready to
establish communication. DTR is placed in the active state by setting the DTR bit of the modem control
register to a high level. DTR is placed in the inactive state either as a result of a master reset, during
loop mode operation, or clearing the DTR bit.
INTRPT
30
33
30
O
Interrupt. When active (high), INTRPT informs the CPU that the ACE has an interrupt to be serviced.
Four conditions that cause an interrupt to be issued are: a receiver error, received data is available or
timed out (FIFO mode only), the transmitter holding register is empty, or an enabled modem status
interrupt. The INTRPT output is reset (deactivated) either when the interrupt is serviced or as a result
of a master reset.
MR
35
39
35
I
Master reset. When active (high), MR clears most ACE registers and sets the state of various output
signals. Refer to Table 2.
OUT1
OUT2
34
31
38
35
34
31
O
Outputs 1 and 2. User-designated outputs that are set to their active low states by setting their
respective modem control register bits (OUT1 and OUT2) high. OUT1 and OUT2 are set to their inactive
(high) states as a result of master reset, during loop mode operations, or by clearing bit 2 (OUT1) or
bit 3 (OUT2) of the modem control register.
Receiver clock. RCLK is the 16
×
baud rate clock for the receiver section of the ACE.
RCLK
9
10
5
I
相關PDF資料
PDF描述
TL16C550CIPFB ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH AUTOFLOW CONTROL
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相關代理商/技術參數(shù)
參數(shù)描述
TL16C550CIPFB 制造商:TI 制造商全稱:Texas Instruments 功能描述:ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH AUTOFLOW CONTROL
TL16C550CIPT 功能描述:UART 接口集成電路 Sngl UART w/16-Byte FIFOs & Aut Flw Ctrl RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
TL16C550CIPTG4 功能描述:UART 接口集成電路 Sngl UART w/16-Byte FIFOs & Aut Flw Ctrl RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
TL16C550CIPTR 功能描述:UART 接口集成電路 Sngl UART w/16-Byte FIFOs & Aut Flw Ctrl RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
TL16C550CIPTRG4 功能描述:UART 接口集成電路 Sngl UART w/16-Byte FIFOs & Aut Flw Ctrl RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
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