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| 型號： | TL16C550BI |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | ASYNCHRONOUS COMMUNICATIONS ELEMENT |
| 中文描述： | 異步通信元 |
| 文件頁數(shù)： | 25/35頁 |
| 文件大?。?/td> | 499K |
| 代理商： | TL16C550BI |
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TL16C550B, TL16C550BI
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136B – JANUARY 1994 – REVISED AUGUST 1996
25
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
interrupt identification register (IIR) (continued)
Table 5. Interrupt Control Functions
INTERRUPT
IDENTIFICATION
REGISTER
BIT 2
PRIORITY
LEVEL
INTERRUPT TYPE
INTERRUPT SOURCE
INTERRUPT RESET
METHOD
BIT 3
BIT 1
BIT 0
0
0
0
1
None
None
None
None
0
1
1
0
1
Receiver line status
Overrun error, parity error,
framing error or break interrupt
Reading the line status register
0
1
0
0
2
Received data available
Receiver data available in the
TL16C450 mode or trigger level
reached in the FIFO mode.
Reading the receiver buffer
register
1
1
0
0
2
Character timeout
indication
No characters have been
removed from or input to the
receiver FIFO during the last
four character times, and there
is at least one character in it
during this time
Reading the receiver buffer
register
0
0
1
0
3
Transmitter holding
register empty
Transmitter holding register–
empty
Reading the interrupt
identification register (if source
of interrupt) or writing into the
transmitter holding register
0
0
0
0
4
Modem status
Clear to send, data set ready,
ring indicator, or data carrier
detect
Reading the modem status
register
line control register (LCR)
The system programmer controls the format of the asynchronous data communication exchange through the
LCR. In addition, the programmer is able to retrieve, inspect, and modify the contents of the LCR; this eliminates
the need for separate storage of the line characteristics in system memory. The contents of this register are
summarized in Table 3 and are described in the following bulleted list.
Bits 0 and 1: These two bits specify the number of bits in each transmitted or received serial character.
These bits are encoded in Table 6.
Table 6. Serial Character Word Length
BIT 1
BIT 0
WORD LENGTH
0
0
5 bits
0
1
6 bits
1
0
7 bits
1
1
8 bits
Bit 2: This bit specifies either one, one and one-half, or two stop bits in each transmitted character. When
bit 2 is cleared, one stop bit is generated in the data. When bit 2 is set, the number of stop bits generated
is dependent on the word length selected with bits 0 and 1. The receiver clocks only the first stop bit,
regardless of the number of stop bits selected. The number of stop bits generated, in relation to word length
and bit 2, is shown in Table 7.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TL16C550 | ASYNCHRONOUS COMMUNICATIONS ELEMENT |
| TL16C550BIN | ASYNCHRONOUS COMMUNICATIONS ELEMENT |
| TL16C550CIN | ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH AUTOFLOW CONTROL |
| TL16C550CIPFB | ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH AUTOFLOW CONTROL |
| TL16C552AMPN | DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TL16C550BIFN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:ASYNCHRONOUS COMMUNICATIONS ELEMENT |
| TL16C550BIN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:ASYNCHRONOUS COMMUNICATIONS ELEMENT |
| TL16C550BIPT | 制造商:TI 制造商全稱:Texas Instruments 功能描述:ASYNCHRONOUS COMMUNICATIONS ELEMENT |
| TL16C550BN | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TL16C550BPT | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
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