![](http://datasheet.mmic.net.cn/390000/TL16C550B----_datasheet_16837966/TL16C550B----_6.png)
==98-11-5==
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==23-6==
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P&Sí í :
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430079
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PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOH
VOL
High-level output voltage
IOH = 1 mA
IOL = 1.6 mA
VCC = 5.25 V,
VCC 5.25 V,
VI = 0 to 5.25 V,
VCC = 5.25 V,
VO = 0 to 5.25 V,
2.4
V
Low-level output voltage
0.4
V
Il
Input current
VSS = 0,
VSS 0,
10
μ
A
I
VSS = 0,
20
OZ
High-impedance-state output current
A
μ
,
ICC
VCC = 5.25 V,
SIN, DSR, DCD, CTS, and RI
All other inputs at
at 0.8 ,
No load on outputs,
A = 25 C,
,
XTAL1 at 4 MHz
Baud
rate =
10
Supply current
V
MA
50 kbit/s
Ci(CLK)
Co(CLK)
Ci
Co
Clock input capacitance
V
TA=25 C
15
20
pF
Clock output capacitance
VCC = 0,
All other terminals grounded
SS = 0,
20
30
pF
Input capacitance
,
6
10
pF
Output capacitance
10
20
pF
*
*
PARAMETER
ALT. SYMBOL
FIGURE
TEST CONDITIONS
MIN
MAX
UNIT
tcR
tcW
tw1
tw2
tw5
tw6
tw7
tw8
tsu1
tsu2
tsu3
th1
th2
th3
th4
th5
th6
th7
td4
td5
td6
td7
td8
td9
td10
td11
Cycle time, read (tw7 + td8 + td9)
Cycle time, write (tw6 + td5 + td6)
Pulse duration, clock high
Pulse duration, clock low
Pulse duration, address strobe low
RC
WC
87
87
ns
ns
tXH
tXL
tADS
tWR
tRD
tMR
tAS
tCS
tDS
tAH
tCH
tWCS
tWA
tDH
tRCS
tRA
tCSW
tAW
tWC
tCSR
tAR
tRC
1
1
f = 9 MHz maximum
f = 9 MHz maximum
40
40
9
ns
ns
ns
2,3
Pulse duration, write strobe
Pulse duration, read strobe
Pulse duration, master reset
2
3
40
40
1
ns
ns
μ
s
ns
ns
Setup time, address valid before ADS
Setup time, chip select valid before ADS
2,3
2,3
8
8
Setup time, data valid before WR1 or WR2
Hold time, address low after ADS
Hold time, chip select valid after ADS
2
15
0
0
ns
ns
ns
2,3
2,3
Hold time, chip select valid after WR1 or WR2
Hold time, address valid after WR1 or WR2
Hold time, data valid after WR1 or WR2
2
2
2
10
10
5
ns
ns
ns
Hold time, chip select valid after RD1 or RD2
Hold time, address valid after RD1 or RD2
3
3
10
20
ns
ns
Delay time, chip select valid before WR1 or WR2
Delay time, address valid before WR1 or WR2
Delay time, write cycle, WR1 or WR2 to ADS
2
2
2
7
7
ns
ns
ns
40
Delay time, chip select valid to RD1 or RD2
Delay time, address valid to RD1 or RD2
Delay time, read cycle, RD1 or RD2
3
3
3
7
7
ns
ns
ns
to ADS
40
Delay time, RD1 or RD2 to data valid
Delay time, RD1 or RD2 to floating data
tRVD
tHZ
3
3
CL = 75 pF
CL = 75 pF
45
20
ns
ns