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參數(shù)資料
| 型號： | TL1466IPMR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 0.5 A SWITCHING CONTROLLER, 800 kHz SWITCHING FREQ-MAX, PQFP64 |
| 封裝： | GREEN, PLASTIC, LQFP-64 |
| 文件頁數(shù)： | 21/26頁 |
| 文件大?。?/td> | 538K |
| 代理商： | TL1466IPMR |
TL1466I
HIGHSPEED/PRECISION SIX CHANNEL
SWITCHING REGULATOR CONTROLLER
SLVS262 FEBRUARY 2000
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
DESCRIPTION
NAME
NO.
DESCRIPTION
BOOT CAP.H1
44
Bootstrap capacitor connection. The connection allows reverse-bias for external PNP transistor of channel 1.
BOOT CAP.L1
45
Bootstrap capacitor connection. The connection allows reverse-bias for external PNP transistor of channel 1.
BOOT CAP.H2
48
Bootstrap capacitor connection. The connection allows reverse-bias for external PNP transistor of channel 2.
BOOT CAP.L2
49
Bootstrap capacitor connection. The connection allows reverse-bias for external PNP transistor of channel 2.
BOOT CAP.H3
54
Bootstrap capacitor connection. The connection allows reverse-bias for external PNP transistor of channel 3
BOOT CAP.L3
55
Bootstrap capacitor connection. The connection allows reverse-bias for external PNP transistor of channel 3
BOOT CAP.L4
58
Bootstrap capacitor connection. The connection allows reverse-bias for external PNP transistor of channel 4.
BOOT CAP.H4
59
Bootstrap capacitor connection. The connection allows reverse-bias for external PNP transistor of channel 4.
BOOT CAP.L5
1
Bootstrap capacitor connection. The connection allows reverse-bias for external PNP transistor of channel 5.
BOOT CAP.H5
2
Bootstrap capacitor connection. The connection allows reverse-bias for external PNP transistor of channel 5.
BOOT CAP.L6
5
Bootstrap capacitor connection. The connection allows reverse-bias for external PNP transistor of channel 6.
BOOT CAP.H6
6
Bootstrap capacitor connection. The connection allows reverse-bias for external PNP transistor of channel 6.
COMP
13
Output regulation voltage monitor terminal. When this terminal voltage drops below VREF voltage (1.5 V),
charging to capacitor connected to SCP terminal (pin 23) is initiated.
COMP1
40
Output regulation voltage monitor terminal (channel 1). When this terminal voltage drops below VREF voltage
(1.5 V) charging to capacitor connected to SCP terminal (pin 23) is initiated.
COMP2
37
Output regulation voltage monitor terminal (channel 2). When this terminal voltage drops below VREF voltage
(1.5 V) charging to capacitor connected to SCP terminal (pin 23) is initiated.
COMP3
34
Output regulation voltage monitor terminal (channel 3). When this terminal voltage drops below VREF voltage
(1.5 V), charging to capacitor connected to SCP terminal (pin 23) is initiated.
COMP4
18
Output regulation voltage monitor terminal (channel 4). When this terminal voltage drops below VREF voltage
(1.5 V) charging to capacitor connected to SCP terminal (pin 23) is initiated.
COMP5
14
Output regulation voltage monitor terminal (channel 5). When this terminal voltage drops below NONINV
INPUT5 terminal voltage 0.55 V, charging to capacitor connected to SCP terminal (pin 23) is initiated.
COMP6
9
Output regulation voltage monitor terminal (channel 6). When this terminal voltage drops below NONINV
INPUT6 terminal voltage 0.55 V, charging to capacitor connected to SCP terminal (pin 23) is initiated.
CT
22
Timing capacitor connection for oscillation frequency setting.
DTC3
31
Dead-time control input for channel 3. The maximum ON duty cycle for OUTPUT3 terminal is determined by
comparing the input voltage of this terminal with the oscillator output (triangle wave).
FEEDBACK1
38
Error amplifier output terminal (channel 1)
FEEDBACK2
35
Error amplifier output terminal (channel 2)
FEEDBACK3
32
Error amplifier output terminal (channel 3)
FEEDBACK4
20
Error amplifier output terminal (channel 4)
FEEDBACK5
17
Error amplifier output terminal (channel 5)
FEEDBACK6
12
Error amplifier output terminal (channel 6)
GND
25
Logic ground
INV INPUT1
39
Error amplifier inverting input terminal (channel 1)
INV INPUT2
36
Error amplifier inverting input terminal (channel 2)
INV INPUT3
33
Error amplifier inverting input terminal (channel 3)
INV INPUT4
19
Error amplifier inverting input terminal (channel 4)
INV INPUT5
16
Error amplifier inverting input terminal (channel 5)
INV INPUT6
11
Error amplifier inverting input terminal (channel 6)
MOS DUTY
24
N-channel MOSFET ON duty cycle setting for the synchronous rectification of channel 1 and 4. The MOSFET
ON duty cycle for the synchronous rectification is determined by the resistor value connected between this
terminal and GND.
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