參數(shù)資料
型號(hào)： TL051AMD
廠商： Texas Instruments, Inc.
英文描述： ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
中文描述： 增強(qiáng)型場(chǎng)效應(yīng)低失調(diào)運(yùn)算放大器
文件頁(yè)數(shù)： 63/65頁(yè)
文件大?。?/td> 1022K
代理商： TL051AMD
TL05x, TL05xA, TL05xY
ENHANCED-JFET LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS178 – FEBRUARY 1997
63
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
macromodel information
Macromodel information provided was derived using Microsim Parts
, the model generation software used
with Microsim PSpice
. The Boyle macromodel (see Note 5) and subcircuit Figure 92 are generated using the
TL05x typical electrical and operating characteristics at T
A
= 25
°
C. Using this information, output simulations
of the following key parameters can be generated to a tolerance of 20% (in most cases):
Maximum positive output voltage swing
Maximum negative output voltage swing
Slew rate
Quiescent power dissipation
Input bias current
Open-loop voltage amplification
Unity-gain frequency
Common-mode rejection ratio
Phase margin
DC output resistance
AC output resistance
Short-circuit output current limit
NOTE 5: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Intergrated Circuit Operational Amplifiers”, IEEE
Journal of Solid-State Circuits,SC-9, 353 (1974).
OUT
+
–
+
–
53
+
–
+
–
+
–
+
–
+
–
+
–
+
–
.SUBCKT TL05x 1 2 3 4 5
C1
C2
DC
DE
DLP
DLN
DP
EGND
FB
+ VLN 0 2.875E6 –3E6 3E6 3E6 –3E6
GA
6
GCM
0
ISS
3
HLIM
90
J1
11
J2
12
R2
6
11
6
5
54
90
92
4
99
7
12
7
53
5
91
90
3
0
99
3.988E–12
15.00E–12
DX
DX
DX
DX
DX
POLY (2) (3,0) (4,0) 0 .5 .5
POLY (5) VB VC VE VLP
0
6
10
0
2
1
9
11
10
DC 300.0E–6
VLIM 1K
10 JX
10 JX
100.0E3
12 292.2E–6
99 6.542E–9
RD1
RD2
R01
R02
RP
RSS
VB
VC
VE
VLIM
VLP
VLN
.MODEL DX D (IS=800.0E–18)
.MODEL JX PJF (IS=15.00E–12 BETA=185.2E–6
+ VTO=–.1)
.ENDS
4
4
8
7
3
10
9
3
54
7
91
0
11
12
5
99
4
99
0
53
4
8
0
92
3.422E3
3.422E3
125
125
11.11E3
666.7E6
DC 0
DC 3
DC 3.7
DC 0
DC 28
DC 28
VCC+
RP
IN –
2
IN+
3
VCC–
VAD
RD1
11
J1
J2
10
RSS
ISS
3
12
RD2
60
VE
54
DE
DP
VC
DC
4
C1
R2
6
9
EGND
VB
FB
C2
GCM
GA
VLIM
8
5
RO1
RO2
HLIM
90
DLP
91
DLN
92
VLN
VLP
99
7
Figure 92. Boyle Macromodel and Subcircuit
PSpice and Partsare trademarks of MicroSim Corporation.
Macromodels, simulation models, or other models provided by TI,
directly or indirectly, are not warranted by TI as fully representing all
of the specification and operating characteristics of the
semiconductor product to which the model relates.
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