參數(shù)資料
型號: TJA1053
廠商: NXP Semiconductors N.V.
元件分類: CAN
英文描述: Fault-tolerant CAN transceiver(容錯(cuò)CAN收發(fā)器)
中文描述: 容錯(cuò)CAN收發(fā)器(容錯(cuò)的CAN收發(fā)器)
文件頁數(shù): 10/16頁
文件大小: 75K
代理商: TJA1053
Philips Semiconductors
APPLICATION HINTS
Systems Laboratory Hamburg, Germany
Fault-tolerant CAN transceiver
V2.0
Page 10 of 16
3.5. Worst Case Max Vcc Supply at Presence of a Dual Short Circuit
The worst case max. Vcc supply current is flowing in case of a
dual short-circuit
of the bus lines
CAN_H and CAN_L to ground. In this case no communication is possible. Nevertheless the
application supply should be able to deliver a proper Vcc for the microcontroller in order to prevent
erroneous operation.
If there is a
separate
voltage regulator available supplying the transceiver exclusively,
no care
has to
be taken on this dual short circuit condition since the transceivers are behaving fail safe in case of
under voltage conditions and the uC is still powered properly by its own supply.
In case of a
shared
voltage supply of transceiver and microcontroller this dual fault condition is
relevant to dimension the required buffer capacitor.
3.5.1. Max Vcc supply current in worst case dual fault condition
I
cc_sc2_dom
= I
cc0_dom
+ I
CANH_sc1_dom
+ I
RTL_sc_dom
( t < 17 bit times )
(7)
I
RTL_sc_dom
= Vcc / R
T
(8)
The 17-bit time limitation is caused by the CAN protocol. Due to the dual fault condition with CANH
and CANL shorted to GND the RxD pin of the transceiver is continuously clamped recessive (CANL to
GND forces CANH operation; CANH is clamped recessive).
The moment the CAN controller starts a transmission, this dominant Start Of Frame bit is not fed back
via RxD and thus forces an error flag due to the bit failure condition (TX Error Counter increment by 8).
This first bit of the error flag again is not reflected at RxD and forces the next error flag (TX Error
Counter + 8).
Latest after 17 bit times, depending on the TX Error Counter Level before starting this transmission,
the CAN controller reaches the Error Passive limit (128) and stops sending dominant bits. Now a
sequence of 25 recessive bits follows (8 Bit Error Delimiter + 3 Bit Intermission + 8 Bit Suspend
Transmission) and the Vcc current becomes reduced to the recessive one.
From now on only single dominant bits (Start Of Frame) followed by 25 recessive bits (Passive Error
Flag + Intermission + Suspend Transmission) are output until the CAN controller enters the Bus Off
State.
So, for dimensioning the Vcc voltage source in this worst case dual failure scenario, up to 17 bit times
might have to be buffered by a bypass capacitor depending on the regulation capabilities of the used
voltage supply.
3.5.2. Example calculation
Max Vcc supply current in worst case dual fault condition:
PCA82C252
:
I
cc_sc2_dom 252
= 35 mA + 100 mA + 5V / 1k =
140 mA max.
(Ex 7.1)
TJA1053
:
I
cc_sc2_dom 1053
= 35 mA + 100 mA + 5V / 1k =
140 mA max.
(Ex 7.2)
TJA1054
:
I
cc_sc2_dom 1054
= 27 mA + 110 mA + 5V / 1k =
142 mA max.
(Ex 7.3)
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TJA1054 Fault-tolerant CAN transceiver(容錯(cuò)CAN收發(fā)器)
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