參數(shù)資料
型號: THS8135PHPG4
廠商: TEXAS INSTRUMENTS INC
元件分類: DAC
英文描述: PARALLEL, WORD INPUT LOADING, 0.015 us SETTLING TIME, 10-BIT DAC, PQFP48
封裝: GREEN, PLASTIC, HTQFP-48
文件頁數(shù): 10/25頁
文件大?。?/td> 522K
代理商: THS8135PHPG4
THS8135
TRIPLE 10BIT, 240 MSPS VIDEO DAC WITH TRILEVEL SYNC AND VIDEO
(ITUR.BT601)COMPLIANT FULL SCALE RANGE
SLAS343A MAY 2001 REVISED JUNE 2002
18
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
analog (DAC) outputs (continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Video mode, full-scale RGB,
AGY
27
28
29.3
Video mode, full-scale RGB,
sync-on-all
ABPb and ARPr
27
28
29.3
Video mode, full-scale YCbCr,
AGY
27
28
29.3
IFS
Video mode, full-scale YCbCr,
sync-on-all
CLK = 80 MSPS, See Note 6
ABPb and ARPr
18
18.67
19.5
mA
IFS
Video mode, ITU-R.BT601RGB,
CLK = 80 MSPS, See Note 6
AGY
30
31.18
32.0
mA
Video mode, ITU-R.BT601RGB,
sync-on-all
ABPb and ARPr
30
31.18
32.3
Video mode, ITU-R.BT601
AGY
30
31.18
32.1
Video mode, ITU-R.BT601
YCbCr, sync-on-all
ABPb and ARPr
20
21.39
22.5
tRDAC
DAC output current rise time
CLK = 80 MSPS, 10 to 90% of full-scale
3.2
3.5
4.2
ns
tFDAC
DAC output current fall time
CLK = 80 MSPS, 10 to 90% of full-scale
3.2
3.5
4.2
ns
td(A)
Analog output delay
Measured from CLK = VIH(min) to 50% of full-scale
transition, See Note 7
4
ns
tS
Analog Output Settling Time
Measured from 50% of full scale transition on output to
output settling, within 2%, See Note 8
15
ns
SFDR
Spurious-free dynamic range
1 MHz, 1 dBFS digital sine input
55
dB
BW
Bandwidth
1 dB
50
MHz
3 dB
100
Eglitch
Glitch energy
Full-scale code transition at 240 MSPS
25
pVs
NOTES:
6. Values at RFS=RFS(nom).
7. This value excludes the digital process delay, tD(D). Limit are from characterization only.
8. Limit from characterization only. Measured on Y channel with other channels not driven.
f Frequency MHz
300
310
320
330
340
350
360
370
380
390
400
0
50
100
150
200
250
300
P
Power
mW
Figure 11. Power vs Clock Frequency, RGB mode, 1-MHz Input Tone on All Channels
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