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參數(shù)資料
| 型號： | THS8083T |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Triple 8-Bit, 80 MSPS, 3.3-V Video and Graphics Digitizer With Digital PLL |
| 中文描述： | 三8位，80 MSPS的，在3.3 V視頻和圖形數(shù)字轉(zhuǎn)換器與數(shù)字鎖相環(huán) |
| 文件頁數(shù)： | 41/61頁 |
| 文件大?。?/td> | 278K |
| 代理商： | THS8083T |
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4
–
1
4 Parameter Measurement Information
All timing diagrams are shown for operation with internal PLL clock at phase 0, and ADCCLK2 non-inverted and
non-divided-by-2.
4.1
Timing Diagram
–
24-Bit Parallel Mode
This mode outputs data on the three channels simultaneously in single-pixel mode. DATACLK1 is at the sampling
clock frequency; output bus B remains high-impedance.
DATACLK
CH1_OUTA[7..0]
CH2_OUTA[7..0]
CH2_OUTB[7..0]
CH1_OUTB[7..0]
CH3_OUTA[7..0]
CH3_OUTB[7..0]
HS
01
02
pix 01
pix 02
ADCCLK2
DHS
tPLH(OE)
tPHL(OE)
tsu(OUT)
th(OUT)
tsu(DHS)
th(DHS)
01
02
01
02
7 ADCCLK2 Cycles Latency
Last Samples From Previous Line
Last Samples From Previous Line
Last Samples From Previous Line
7 ADCCLK2
Cycles Latency
<DHS_MODE> = 1
–
> Width
Equal to Width of HS Input
<DHS_MODE> = 0
–
> DHS
Width is 1 ADCCLK2 Period
(DHS_POL = 0
Assumed-Inverted
Polarity Otherwise)
OE
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