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參數(shù)資料
| 型號： | THS8083APZP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | GREEN, PLASTIC, HTQFP-100 |
| 文件頁數(shù)： | 3/63頁 |
| 文件大?。?/td> | 320K |
| 代理商： | THS8083APZP |
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26
1.7
THS8083A Terminal Functions Order (Continued)
TERMINAL
I/O/B
TYPE
DESCRIPTION
NAME
NO.
I/O/B
TYPE
DESCRIPTION
CLOCK I/O
XTL1_MCLK
20
I
A
Master crystal connection 1 (connects 14.318-MHz crystal) or master clock input (at
14.318 MHz)
XTL2
22
O
A
Master crystal connection 2 (connects 14.318-MHz crystal)
DATACLK1
54
O
D
1st clock output: DATACLK1
The rising edge of this clock can be used by an external device to clock in THS8083A output
data in all modes (see output timing diagrams in Section 4 for more details).
ADCCLK2
53
O
D
2nd clock output: ADCCLK
This clock output is equal to the clock of the ADC converter, optionally inverted and/or
divided-by-2.
DTOCLK3
52
O
D
3rd clock output: DTOCLK.
This clock output is the output of the DTO.
EXT_ADCCLK
56
I
D
External clock input for A/D channels, at pixel clock frequency
ANALOG SIGNAL I/O
CH1_IN
81
I
A
Analog input channel 1. Since this channel includes the composite sync slicer and is not
downsampled in 4:2:2 mode, this channel should be used for green or luminance input, if any
of these features are used.
CH2_IN
88
I
A
Analog input channel 2. In YUV 4:2:2 sampling mode, Pb should be connected to this input to
generate a ITU.BT-601 style output.
CH3_IN
95
I
A
Analog input channel 3. In YUV 4:2:2 sampling mode, Pr should be connected to this input to
generate a ITU.BT-601 style output.
VREFBO_CH1
82
B
A
Reference voltage bottom output channel 1. In normal operation: output. For a specific
configuration, this terminal becomes an input terminal (see Powerdown section in Functional
Description).
VREFTO_CH1
83
B
A
Reference voltage top output channel 1. In normal operation it is an output. For a specific
configuration, this terminal becomes an input terminal (see Powerdown section in Functional
Description).
VREFBO_CH2
89
B
A
Reference voltage bottom output channel 2. See VREFBO_CH1.
VREFTO_CH2
90
B
A
Reference voltage top output channel 2. See VREFTO_CH1.
VREFBO_CH3
96
B
A
Reference voltage bottom output channel 3. See VREFBO_CH1.
VREFTO_CH3
97
B
A
Reference voltage top output channel 3. See VREFTO_CH1.
VMID
73
B
A
Midlevel input range (input common mode). In normal operation it is an output. For a specific
configuration, this terminal becomes an input terminal (see Powerdown section in Functional
Description).
VCM
72
O
A
Common mode voltage output (approximately 1.5 V)
DIGITAL SIGNAL I/O
CH1A0
42
O
D
Display output channel 1, bus A, bit 0 (LSB)
CH1A1
43
O
D
Display output channel 1, bus A, bit 1
CH1A2
44
O
D
Display output channel 1, bus A, bit 2
CH1A3
45
O
D
Display output channel 1, bus A, bit 3
CH1A4
46
O
D
Display output channel 1, bus A, bit 4
CH1A5
47
O
D
Display output channel 1, bus A, bit 5
CH1A6
48
O
D
Display output channel 1, bus A, bit 6
CH1A7
49
O
D
Display output channel 1, bus A, bit 7 (MSB)
CH1B0
63
O
D
Display output channel 1, bus B, bit 0 (LSB)
CH1B1
64
O
D
Display output channel 1, bus B, bit 1
I = input to device: O = output from device B = bidirectional
A = analog pin: D = digital pin
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| THS8083APZP | 制造商:Texas Instruments 功能描述:8BIT ADC 80MSPS TRIPLE SMD 8083 |
| THS8083APZPG4 | 功能描述:視頻模擬/數(shù)字化轉(zhuǎn)換器集成電路 Tr 8B 95MSPS 3.3V Vid & Graphics Dig RoHS:否 制造商:Texas Instruments 輸入信號類型:Differential 轉(zhuǎn)換器數(shù)量:1 ADC 輸入端數(shù)量:4 轉(zhuǎn)換速率:3 Gbps 分辨率:8 bit 結(jié)構(gòu): 輸入電壓:3.3 V 接口類型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel |
| THS8083CPZP | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| THS8083EVM | 制造商:Texas Instruments 功能描述:THS8083EVM - Bulk |
| THS8083T | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Triple 8-Bit, 80 MSPS, 3.3-V Video and Graphics Digitizer With Digital PLL |
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