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參數(shù)資料
| 型號： | THS7303PWRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 音頻／視頻放大 |
| 英文描述： | 3 CHANNEL, VIDEO AMPLIFIER, PDSO20 |
| 封裝： | GREEN, PLASTIC, TSSOP-20 |
| 文件頁數(shù)： | 40/60頁 |
| 文件大?。?/td> | 1980K |
| 代理商： | THS7303PWRG4 |
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SLOS479B
– OCTOBER 2005 – REVISED MARCH 2011
EXAMPLE: READING FROM THE THS7303
The read operation consists of two phases. The first phase is the address phase, where an I2C master initiates a
write operation to the THS7303 by generating a start condition (S) followed by the THS7303 I2C address in MSB
first bit order, followed by a '0' to indicate a write cycle. After receiving acknowledges from the THS7303, the
master presents the sub-address (channel) of the register it wants to read. After the cycle is acknowledged (A),
the master terminates the cycle immediately by generating a stop condition (P).
The second phase is the data phase. In this phase, an I2C master initiates a read operation to the THS7303 by
generating a start condition followed by the THS7303 I2C address in MSB first bit order, followed by a '1' to
indicate a read cycle. After an acknowledge from the THS7303, the I2C master receives one byte of data from
the THS7303. After the data byte has been transferred from the THS7303 to the master, the master generates a
not acknowledge (A) followed by a stop. As with the write function, in order to read all channels, steps 1 through
11 must be repeated for each channel desired.
Example of THS7303 Read Phase 1:
Step 1
0
I2C Start (Master)
S
Step 2
7
6
5
4
3
2
1
0
I2C General Address (Master)
0
1
0
1
X
0
Where each X logic state is defined by I2C A1 and I2C A0 pins being tied to either VS+ or GND.
Step 3
9
I2C Acknowledge (Slave)
A
Step 4
7
6
5
4
3
2
1
0
I2C Read Channel Address (Master)
0
Addr
Where Addr is determined by the values shown in Table 2.
Step 5
9
I2C Acknowledge (Slave)
A
Step 6
0
I2C Start (Master)
P
Example of THS7303 Read Phase 2:
Step 7
0
I2C Start (Master)
S
Step 8
7
6
5
4
3
2
1
0
I2C General Address (Master)
0
1
0
1
X
1
Where each X logic state is defined by I2C A1 and I2C A0 pins being tied to either VS+ or GND.
Step 9
9
I2C Acknowledge (Slave)
A
Step 10
7
6
5
4
3
2
1
0
I2C Read Data (Slave)
Data
Copyright
2005–2011, Texas Instruments Incorporated
45
Product Folder Link(s): THS7303
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