參數(shù)資料
型號: THS6132RGW
廠商: Texas Instruments, Inc.
英文描述: HIGH EFFICIENCY CLASS - G ADSL LINE DRIVER
中文描述: 高效類-摹ADSL線路驅(qū)動(dòng)器
文件頁數(shù): 6/21頁
文件大?。?/td> 339K
代理商: THS6132RGW
THS6132
SLLS543A
SEPTEMBER 2002
REVISED FEBRUARY 2003
www.ti.com
6
ELECTRICAL CHARACTERISTICS (continued)
over recommended operating free-air temperature range, TA = 25
°
C,VCC(H) =
±
15 V, VCC(L) =
±
5 V RF = 1.5 k
, Gain = +10, Full Bias Mode, RL
= 50
(unless otherwise noted)
INPUT CHARACTERISTICS
PARAMETER
TEST CONDITIONS
TA = 25
°
C
TA = full range
TA = 25
°
C
MIN
±
2.7
±
2.6
TYP
±
3.0
MAX
UNIT
VCC(L) =
±
5 V
V
ICR
Input common
mode voltage range(1)
In ut common mode voltage range( )
V
VCC(L) =
±
6 V
VCC
(L)=
±
5 V
VCC(L) =
±
6 V
±
4.0
±
2.5
±
3.5
67
REF pin input voltage range
V
CMRR
Common moderejectionratio
Common-mode rejection ratio
VCC(L) =
5 V,
±
±
6 V
TA = 25
°
C
TA = full range
60
57
dB
R
I
Inputresistance
Input resistance
+ Input
Input
800
45
1.2
k
pF
C
I
Differential Input capacitance
(1) To conserve as much power as possible, the nput stage of the THS6132 s powered from the VCC(L) supplies and s imited by the VCC(L) supply
voltage. For Class-AB operation, connect the VCC(L) supplies to VCC(H).
LOGIC CONTROL CHARACTERISTICS
PARAMETER
VIH
Bias pin voltage for logic 1
VIL
Bias pin voltage for logic 0
IIH
Bias pin current for logic 1
IIL
Bias pin current for logic 0
Transition time
logic 0 to logic 1(1)
Transition time
logic 1 to logic 0(1)
DGND useable range
TEST CONDITIONS
Relative to DGND pin voltage
Relative to DGND pin voltage
VIH = 5 V, DGND = 0 V
VIL = 0 V, DGND = 0 V
MIN
2.0
TYP
MAX
UNIT
V
V
μ
A
μ
A
μ
s
μ
s
V
0.8
0.2
0.2
0.1
0.1
0.1
0.2
VCC(H)
+VCC(H)
5
(1) Transition time is defined as the time from when the logic signal is applied to the time when the supply current has reached half its final value.
LOGIC TABLE
BIAS-1
1
1
1
0
0
BIAS-2
1
0
0
1
0
BIAS-3
X(1)
1
0
X(1)
X(1)
FUNCTION
Full bias mode
Mid bias mode
Low bias mode
Terminate mode
Shutdown mode
DESCRIPTION
Amplifiers ON with lowest distortion possible
Amplifiers ON with power savings with a reduction in distortion performance
Amplifiers ON with enhanced power savings and a reduction of distortion performance
Lowest power state with +Vin pins internally connect to REF pin and output has ow mpedance
Amplifiers OFF and output has high impedance
(1)X is used to denote a logic state of either 1 or 0.
NOTE:The default state for all logic pins is a logic one (1).
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