參數(shù)資料
型號(hào): THS6072EVM
廠商: Texas Instruments, Inc.
英文描述: LOW-POWER ADSL DIFFERENTIAL RECEIVER
中文描述: 低功耗寬帶差分接收機(jī)
文件頁(yè)數(shù): 20/24頁(yè)
文件大小: 385K
代理商: THS6072EVM
THS6072
LOW-POWER ADSL DIFFERENTIAL RECEIVER
SLOS290A – FEBRUARY 2000 – REVISED APRIL 2000
20
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
general PowerPAD design considerations (continued)
The next consideration is the package constraints. The two sources of heat within an amplifier are quiescent
power and output power. The designer should never forget about the quiescent heat generated within the
device, especially multiamplifier devices. Because these devices have linear output stages (Class A-B), most
of the heat dissipation is at low output voltages with high output currents. Figure 48 and Figure 49 show this
effect, along with the quiescent heat, with an ambient air temperature of 50
°
C. Obviously, as the ambient
temperature increases, the limit lines shown will drop accordingly. The area under each respective limit line is
considered the safe operating area. Any condition above this line will exceed the amplifier’s limits and failure
may result. When using V
CC
=
±
5 V, there is generally not a heat problem, even with SOIC packages. But, when
using
V
CC
=
±
15 V, the SOIC package is severely limited in the amount of heat it can dissipate. The other key factor
when looking at these graphs is how the devices are mounted on the PCB. The PowerPAD devices are
extremely useful for heat dissipation. But, the device should always be soldered to a copper plane to fully use
the heat dissipation properties of the PowerPAD. The SOIC package, on the other hand, is highly dependent
on how it is mounted on the PCB. As more trace and copper area is placed around the device,
θ
JA
decreases
and the heat dissipation capability increases. The currents and voltages shown in these graphs are for the total
package.
Figure 48
Package With
θ
JA
64
°
C/W
SO-8 Package
θ
JA = 98
°
C/W
High-K Test PCB
VCC =
±
5 V
TJ = 150
°
C
TA = 50
°
C
Both Channels
100
80
40
0
0
1
| VO | – RMS Output Voltage – V
2
3
IO
|
140
180
200
4
5
160
120
60
20
|
Maximum Output
Current Limit Line
THS6072
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
SO-8 Package
θ
JA = 167
°
C/W
Low-K Test PCB
Safe Operating Area
Figure 49
100
10
0
3
| VO | – RMS Output Voltage – V
6
9
1000
12
15
Maximum Output
Current Limit Line
IO
|
|
VCC =
±
15 V
TJ = 150
°
C
TA = 50
°
C
Both Channels
THS6072
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
1
SO-8 Package
θ
JA = 167
°
C/W
Low-K Test PCB
DGN Package
θ
JA = 58.4
°
C/W
Safe Operating Area
SO-8 Package
θ
JA = 98
°
C/W
High-K Test PCB
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