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參數(shù)資料
| 型號： | THS5671AIPWRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DAC |
| 英文描述： | PARALLEL, WORD INPUT LOADING, 0.035 us SETTLING TIME, 14-BIT DAC, PDSO28 |
| 封裝： | GREEN, PLASTIC, TSSOP-28 |
| 文件頁數(shù)： | 28/33頁 |
| 文件大小： | 1013K |
| 代理商： | THS5671AIPWRG4 |
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THS5671A
14BIT, 125 MSPS, CommsDAC
DIGITALTOANALOG CONVERTER
SLAS201A DECEMBER 1999 REVISED SEPTEMBER 2002
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range, AVDD = 5 V,
DVDD = 5 V, IOUTFS = 20 mA (unless otherwise noted)
dc specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Resolution
14
Bits
DC accuracy
INL
Integral nonlinearity
TA = 40°C to 85°C
7
±2.5
7
LSB
DNL
Differential nonlinearity
TA = 40°C to 85°C
3.5
±2
3.5
LSB
Monotonicity
At 11-bit level
Monotonic
Analog output
Offset error
0.02
%FSR
Gain error
Without internal reference
2.3
%FSR
Gain error
With internal reference
1.3
%FSR
Full scale output current
2
20
mA
Output compliance range
AVDD = 5 V, IOUTFS = 20 mA
1
1.25
V
Output resistance
300
k
Output capacitance
5
pF
Reference output
Reference voltage
1.18
1.22
1.32
V
Reference output current§
100
nA
Reference input
VEXTIO
Input voltage range
0.1
1.25
V
Input resistance
1
M
Small signal bandwidth
Without CCOMP1
1.3
MHz
Input capacitance
100
pF
Temperature coefficients
Offset drift
0
Gain drift
Without internal reference
±40
ppm of
FSR/ C
Gain drift
With internal reference
±120
ppm of
FSR/
°C
Reference voltage drift
±35
Power supply
AVDD
Analog supply voltage
4.5
5
5.5
V
DVDD
Digital supply voltage
3
5.5
V
IAVDD
Analog supply current
25
30
mA
IAVDD
Sleep mode supply current
Sleep mode
3
5
mA
IDVDD
Digital supply current#
5
6
mA
Power dissipation||
AVDD = 5 V, DVDD = 5 V, IOUTFS = 20 mA
175
mW
AVDD
Power supply rejection ratio
±0.4
%FSR/V
DVDD
Power supply rejection ratio
±0.025
%FSR/V
Operating range
40
85
°C
Measured at IOUT1 in virtual ground configuration.
Nominal full-scale current IOUTFS equals 32X the IBIAS current.
§ Use an external buffer amplifier with high impedance input to drive any external load.
Reference bandwidth is a function of external cap at COMP1 pin and signal level.
# Measured at fCLK = 50 MSPS and fOUT= 1 MHz.
|| Measured for 50 RLOAD at IOUT1 and IOUT2, fCLK = 50 MSPS and fOUT = 20 MHz.
Specifications subject to change
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