參數(shù)資料
型號(hào)： THS5651AIPWR
廠商： TEXAS INSTRUMENTS INC
元件分類： DAC
英文描述： PARALLEL, WORD INPUT LOADING, 0.035 us SETTLING TIME, 10-BIT DAC, PDSO28
封裝： PLASTIC, TSSOP-28
文件頁(yè)數(shù)： 11/33頁(yè)
文件大?。?/td> 948K
代理商： THS5651AIPWR
THS5651A
10BIT, 125 MSPS, CommsDAC
DIGITALTOANALOG CONVERTER
SLAS260A FEBRUARY 2000 REVISED SEPTEMBER 2002
19
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
analog current outputs
Figure 32 shows a simplified schematic of the current source array output with corresponding switches.
Differential PMOS switches direct the current of each individual PMOS current source to either the positive
output node IOUT1 or its complementary negative output node IOUT2. The output impedance is determined
by the stack of the current sources and differential switches, and is typically >300 k
in parallel with an output
capacitance of 5 pF.
Output nodes IOUT1 and IOUT2 have a negative compliance voltage of 1 V, determined by the CMOS process.
Beyond this value, transistor breakdown may occur, resulting in reduced reliability of the THS5651A device. The
positive output compliance depends on the full-scale output current IOUTFS and positive supply voltage AVDD.
The positive output compliance equals 1.25 V for AVDD = 5 V and IOUTFS = 20 mA. Exceeding the positive
compliance voltage adversely affects distortion performance and integral nonlinearity. The optimum distortion
performance for a single-ended or differential output is achieved when the maximum full-scale signal at IOUT1
and IOUT2 does not exceed 0.5 V (e.g. when applying a 50-
doubly terminated load for 20 mA full-scale output
current). Applications requiring the THS5651A output (i.e., OUT1 and/or OUT2) to extend its output compliance
should size RLOAD accordingly.
AVDD
Current Source Array
IOUT1
IOUT2
RLOAD
Current
Sources
Switches
Figure 32. Equivalent Analog Current Output
Figure 33(a) shows the typical differential output configuration with two external matched resistor loads. The
nominal resistor load of 50
will give a differential output swing of 2 VPP when applying a 20-mA full-scale output
current. The output impedance of the THS5651A depends slightly on the output voltage at nodes IOUT1 and
IOUT2. Consequently, for optimum dc integral nonlinearity, the configuration of Figure 33(b) should be chosen.
In this IV configuration, terminal IOUT1 is kept at virtual ground by the inverting operational amplifier. The
complementary output should be connected to ground to provide a dc current path for the current sources
switched to IOUT2. Note that the INL/DNL specifications for the THS5651A are measured with IOUT1
maintained at virtual ground. The amplifier’s maximum output swing and the DAC’s full-scale output current
determine the value of the feedback resistor RFB. Capacitor CFB filters the steep edges of the THS5651A current
output, thereby reducing the operational amplifier slew-rate requirements. In this configuration, the op amp
should operate on a dual supply voltage due to its positive and negative output swing. Node IOUT1 should be
selected if a single-ended unipolar output is desirable.
相關(guān)PDF資料
PDF描述
THS5651AIPWRG4 PARALLEL, WORD INPUT LOADING, 0.035 us SETTLING TIME, 10-BIT DAC, PDSO28
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THS5651AIDWG4 PARALLEL, WORD INPUT LOADING, 0.035 us SETTLING TIME, 10-BIT DAC, PDSO28
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