參數(shù)資料
型號(hào): THS5651AIDWG4
廠商: TEXAS INSTRUMENTS INC
元件分類: DAC
英文描述: PARALLEL, WORD INPUT LOADING, 0.035 us SETTLING TIME, 10-BIT DAC, PDSO28
封裝: GREEN, PLASTIC, SOIC-28
文件頁(yè)數(shù): 13/31頁(yè)
文件大?。?/td> 771K
代理商: THS5651AIDWG4
THS5651A
10-BIT, 125 MSPS, CommsDAC
DIGITAL-TO-ANALOG CONVERTER
SLAS260A – FEBRUARY 2000 – REVISED SEPTEMBER 2002
20
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
IOUT2
IOUT1
IOUT2
IOUT1
VOUT
100
+
RFB
+)
–)
VOUT
+)
–)
50
(a)
(b)
50
CFB
THS4001
THS4011
Figure 33. Differential and Single-Ended Output Configuration
The THS5651A can be easily configured to drive a doubly terminated 50-
cable. Figure 34(a) shows the
single-ended output configuration, where the output current IOUT1 flows into an equivalent load resistance of
25
. Node IOUT2 should be connected to ground or terminated with a resistor of 25 . Differential-to-single
conversion (e.g., for measurement purposes) can be performed using a properly selected RF transformer, as
shown in Figure 34(b). This configuration provides maximum rejection of common-mode noise sources and
even order distortion components, thereby doubling the power to the output. The center tap on the primary side
of the transformer is connected to AGND, enabling a dc current flow for both IOUT1 and IOUT2. Note that the
ac performance of the THS5651A is optimum and specified using this differential transformer coupled output,
limiting the voltage swing at IOUT1 and IOUT2 to
±0.5 V.
IOUT2
IOUT1
VOUT
IOUT2
IOUT1
VOUT
50
100
(a)
(b)
25
50
50
50
50
1:1
Figure 34. Driving a Doubly Terminated 50
Cable
相關(guān)PDF資料
PDF描述
THS5651AIDWRG4 PARALLEL, WORD INPUT LOADING, 0.035 us SETTLING TIME, 10-BIT DAC, PDSO28
THS5651IDWR PARALLEL, WORD INPUT LOADING, 0.035 us SETTLING TIME, 10-BIT DAC, PDSO28
THS5651IPW PARALLEL, WORD INPUT LOADING, 0.035 us SETTLING TIME, 10-BIT DAC, PDSO28
THS5651IPWR PARALLEL, WORD INPUT LOADING, 0.035 us SETTLING TIME, 10-BIT DAC, PDSO28
THS5651IDW PARALLEL, WORD INPUT LOADING, 0.035 us SETTLING TIME, 10-BIT DAC, PDSO28
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