• 參數(shù)資料
    型號: THS4221DGK
    廠商: TEXAS INSTRUMENTS INC
    元件分類: 音頻/視頻放大
    英文描述: 1 CHANNEL, VIDEO PREAMPLIFIER, PDSO8
    封裝: GREEN, PLASTIC, MSOP-8
    文件頁數(shù): 11/38頁
    文件大?。?/td> 1219K
    代理商: THS4221DGK
    THS4221, THS4225
    THS4222, THS4226
    SLOS399G AUGUST 2002 REVISED JANUARY 2004
    www.ti.com
    19
    the feedback resistor directly under the package on
    the other side of the board between the output and
    inverting input pins. Even with a low parasitic
    capacitance
    shunting
    the
    external
    resistors,
    excessively high resistor values can create significant
    time constants that can degrade performance. Good
    axial metal-film or surface-mount resistors have
    approximately 0.2 pF in shunt with the resistor. For
    resistor values > 2.0 k, this parasitic capacitance can
    add a pole and/or a zero below 400 MHz that can
    effect circuit operation. Keep resistor values as low as
    possible, consistent with load driving considerations.
    It has been suggested here that a good starting point
    for design would be set the Rf be set to 1.3 k for
    low-gain, noninverting applications. Doing this
    automatically keeps the resistor noise terms low, and
    minimize the effect of their parasitic capacitance.
    4. Connections to other wideband devices on the
    board may be made with short direct traces or
    through onboard transmission lines. For short
    connections, consider the trace and the input to the
    next device as a lumped capacitive load. Relatively
    wide traces (50 mils to 100 mils) should be used,
    preferably with ground and power planes opened up
    around them. Estimate the total capacitive load and
    set RISO from the plot of recommended RISO vs
    Capacitive Load. Low parasitic capacitive loads
    (<4 pF) may not need an R(ISO), since the THS4222
    is nominally compensated to operate with a 2-pF
    parasitic load. Higher parasitic capacitive loads
    without an R(ISO) are allowed as the signal gain
    increases (increasing the unloaded phase margin). If
    a long trace is required, and the 6-dB signal loss
    intrinsic to a doubly-terminated transmission line is
    acceptable, implement a matched impedance
    transmission line using microstrip or stripline
    techniques (consult an ECL design handbook for
    microstrip and stripline layout techniques). A 50-
    environment is normally not necessary onboard, and
    in fact a higher impedance environment improves
    distortion as shown in the distortion versus load plots.
    With a characteristic board trace impedance defined
    based on board material and trace dimensions, a
    matching series resistor into the trace from the output
    of the THS4222 is used as well as a terminating shunt
    resistor at the input of the destination device.
    Remember also that the terminating impedance is the
    parallel combination of the shunt resistor and the input
    impedance of the destination device: this total
    effective impedance should be set to match the trace
    impedance. If the 6-dB attenuation of a doubly
    terminated transmission line is unacceptable, a long
    trace can be series-terminated at the source end only.
    Treat the trace as a capacitive load in this case and set
    the series resistor value as shown in the plot of R(ISO)
    vs Capacitive Load. This setting does not preserve
    signal integrity or a doubly-terminated line. If the input
    impedance of the destination device is low, there is
    some signal attenuation due to the voltage divider
    formed by the series output into the terminating
    impedance.
    5. Socketing a high speed part like the THS4222 is
    not recommended. The additional lead length and
    pin-to-pin capacitance introduced by the socket can
    create a troublesome parasitic network which can
    make it almost impossible to achieve a smooth, stable
    frequency response. Best results are obtained by
    soldering the THS4222 onto the board.
    PowerPAD DESIGN CONSIDERATIONS
    The THS4222 family is available in a thermally-enhanced
    PowerPAD family of packages. These packages are
    constructed using a downset leadframe upon which the die
    is mounted [see Figure 36(a) and Figure 36(b)]. This
    arrangement results in the lead frame being exposed as a
    thermal pad on the underside of the package [see
    Figure 36(c)]. Because this thermal pad has direct thermal
    contact with the die, excellent thermal performance can be
    achieved by providing a good thermal path away from the
    thermal pad.
    The PowerPAD package allows for both assembly and
    thermal management in one manufacturing operation.
    During the surface-mount solder operation (when the
    leads are being soldered), the thermal pad can also be
    soldered to a copper area underneath the package.
    Through the use of thermal paths within this copper area,
    heat can be conducted away from the package into either
    a ground plane or other heat dissipating device.
    The PowerPAD package represents a breakthrough in
    combining the small area and ease of assembly of surface
    mount with the heretofore awkward mechanical methods
    of heatsinking.
    Figure 36. Views of Thermally Enhanced
    Package
    DIE
    Side View (a)
    DIE
    End View (b)
    Thermal
    Pad
    Bottom View (c)
    Although there are many ways to properly heatsink the
    PowerPAD package, the following steps illustrate the
    recommended approach.
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