參數(shù)資料
      型號: THS4221DBVT
      廠商: TEXAS INSTRUMENTS INC
      元件分類: 音頻/視頻放大
      英文描述: 1 CHANNEL, VIDEO PREAMPLIFIER, PDSO5
      封裝: GREEN, PLASTIC, SOT-23, 5 PIN
      文件頁數(shù): 10/38頁
      文件大?。?/td> 1219K
      代理商: THS4221DBVT
      THS4221, THS4225
      THS4222, THS4226
      SLOS399G AUGUST 2002 REVISED JANUARY 2004
      www.ti.com
      18
      NOISE ANALYSIS
      High slew rates, stable unity gain, voltage-feedback
      operational amplifiers usually achieve their slew rate at the
      expense of a higher input noise voltage. The input-referred
      voltage noise, and the two input-referred current noise
      terms, combine to give low output noise under a wide
      variety of operating conditions. Figure 35 shows the
      amplifier noise analysis model with all the noise terms
      included. In this model, all noise terms are taken to be
      noise voltage or current density terms in either nV/√Hz or
      pA/√Hz.
      _
      +
      Rf
      4kT = 1.6E20J
      at 290K
      THS4222 FAMILY
      IBN
      EO
      ERF
      RS
      ERS
      IBI
      Rg
      ENI
      4kTRS
      4kT
      Rg
      4kTRf
      Figure 35. Noise Analysis Model
      The total output shot noise voltage can be computed as the
      square of all squares output noise voltage contributors.
      Equation 1 shows the general form for the output noise
      voltage using the terms shown in Figure 35:
      EO +
      E 2
      NI ) IBNRS
      2
      ) 4kTRS NG2 ) IBIRf
      2
      ) 4kTRfNG
      Dividing this expression by the noise gain (NG=(1+ Rf/Rg))
      gives the equivalent input-referred spot noise voltage at
      the noninverting input, as shown in equation 2:
      E
      O +
      E 2
      NI ) IBNRS
      2 ) 4kTR
      S )
      I
      BIRf
      NG
      2
      )
      4kTR
      f
      NG
      Driving Capacitive Loads
      One of the most demanding, and yet very common, load
      conditions for an op amp is capacitive loading. Often, the
      capacitive load is the input of an A/D converter, including
      additional
      external
      capacitance,
      which
      may be
      recommended to improve A/D linearity. A high-speed, high
      open-loop gain amplifier like the THS4222 can be very
      susceptible to decreased stability and closed-loop
      response peaking when a capacitive load is placed directly
      on the output pin. When the amplifier’s open-loop output
      resistance is considered, this capacitive load introduces
      an additional pole in the signal path that can decrease the
      phase margin. When the primary considerations are
      frequency response flatness, pulse response fidelity, or
      distortion, the simplest and most effective solution is to
      isolate the capacitive load from the feedback loop by
      inserting a series isolation resistor between the amplifier
      output and the capacitive load. This does not eliminate the
      pole from the loop response, but rather shifts it and adds
      a zero at a higher frequency. The additional zero acts to
      cancel the phase lag from the capacitive load pole, thus
      increasing the phase margin and improving stability.
      BOARD LAYOUT
      Achieving optimum performance with a high frequency
      amplifier like the THS4222 requires careful attention to
      board layout parasitics and external component types.
      Recommendations that optimize performance include:
      1. Minimize parasitic capacitance to any ac ground
      for all of the signal I/O pins. Parasitic capacitance on
      the output and inverting input pins can cause
      instability: on the noninverting input, it can react with
      the source impedance to cause unintentional band
      limiting. To reduce unwanted capacitance, a window
      around the signal I/O pins should be opened in all of
      the ground and power planes around those pins.
      Otherwise, ground and power planes should be
      unbroken elsewhere on the board.
      2. Minimize the distance (< 0.25”) from the power
      supply pins to high frequency 0.1-F decoupling
      capacitors. At the device pins, the ground and power
      plane layout should not be in close proximity to the
      signal I/O pins. Avoid narrow power and ground traces
      to minimize inductance between the pins and the
      decoupling capacitors. The power supply connections
      should always be decoupled with these capacitors.
      Larger (2.2-F to 6.8-F) decoupling capacitors,
      effective at lower frequency, should also be used on
      the main supply pins. These may be placed somewhat
      farther from the device and may be shared among
      several devices in the same area of the PC board.
      3. Careful selection and placement of external
      components will preserve the high frequency
      performance of the THS4222. Resistors should be
      a very low reactance type. Surface-mount resistors
      work best and allow a tighter overall layout. Metal-film
      and carbon composition, axially-leaded resistors can
      also provide good high frequency performance.
      Again, keep their leads and PC board trace length as
      short as possible. Never use wire wound type
      resistors in a high frequency application. Since the
      output pin and inverting input pin are the most
      sensitive to parasitic capacitance, always position the
      feedback and series output resistor, if any, as close as
      possible to the output pin. Other network components,
      such as noninverting input termination resistors,
      should also be placed close to the package. Where
      double-side component mounting is allowed, place
      (1)
      (2)
      相關PDF資料
      PDF描述
      THS4221D 1 CHANNEL, VIDEO PREAMPLIFIER, PDSO8
      THS4221DR 1 CHANNEL, VIDEO PREAMPLIFIER, PDSO8
      THS4221DGN 1 CHANNEL, VIDEO PREAMPLIFIER, PDSO8
      THS4221DGNR 1 CHANNEL, VIDEO PREAMPLIFIER, PDSO8
      THS4221DBVR 1 CHANNEL, VIDEO PREAMPLIFIER, PDSO5
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