參數(shù)資料
型號: THS1230CDWR
廠商: Texas Instruments
文件頁數(shù): 4/25頁
文件大小: 0K
描述: IC 12 BIT 30 MSPS A/D 28-SOIC
產(chǎn)品培訓模塊: Data Converter Basics
標準包裝: 1,000
位數(shù): 12
采樣率(每秒): 30M
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 220mW
電壓電源: 模擬和數(shù)字
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 28-SOIC
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 1 個差分,單極
配用: 296-10012-ND - EVALUATION MODULE FOR THS1230
www.ti.com
AIN
0
4095
2V
MODE 2, CON[1:0] = 10
OUTPUT
CODE
AIN
0
4095
1V
MODE 1, CON[1:0] = 01
OUTPUT
CODE
AIN+
Signal Processing Chain (Sample and Hold, ADC)
THS1230
SLAS291B – OCTOBER 2000 – REVISED MARCH 2004
Table 1. Input Modes of Operation
MODE
CON1
CON0
MODE OF OPERATION
0
Device powered down
1
0
1
Differential mode
× 1
2
1
0
Differential mode
× 0.5
3
1
Not used
Modes 1 and 2 are shown in Figure 14.
Figure 14. Input Mode Configurations
The gain of the sample and hold changes with the CON1 and the CON0 inputs. Table 2 shows the gain of the
sample and hold and the levels applied at the AIN+ and AIN– analog inputs for Mode 1 and Mode 2. The
common mode level for the two analog inputs is at AVDD/2.
Table 2. Input Mode Switching
(AIN+) – (AIN–)
MODE
CON1
CON0
S/H GAIN
MIN
MAX
1
0
1
–1 V
1 V
×1
2
1
0
–2 V
2 V
×0.5
Table 2 assumes that the delta in ADC reference voltages VREFT and VREFB is set to 1 V, i.e., VREFT – VREFB = 1
V. Note that VREFB and VREFT can be set externally, which will scale the numbers given in this table.
The user-chosen operating configuration and reference voltages determine what input signal voltage range the
THS1230 can handle.
The following sections explain both the internal signal flow of the device and how the input signal span is related
to the ADC reference voltages, as well as the ways in which the ADC reference voltages can be buffered
internally or externally applied.
Figure 15 shows the signal flow through the sample and hold unit and the PGA to the ADC core.
12
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