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參數(shù)資料
| 型號(hào)： | THS1215IPWRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類(lèi)： | ADC |
| 英文描述： | 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28 |
| 封裝： | GREEN, PLASTIC, TSSOP-28 |
| 文件頁(yè)數(shù)： | 8/22頁(yè) |
| 文件大?。?/td> | 391K |
| 代理商： | THS1215IPWRG4 |
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AGND
1
CON1
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CON0
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EXTREF
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AIN+
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AIN
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AGND
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AVDD
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REFT
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REFB
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OVRNG
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D11
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D10
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D9
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D8
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D7
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D6
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D5
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DGND
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DVDD
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D4
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D3
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D2
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D1
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D0
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OE
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CLKVDD
27
CLK
28
U1
THS1215PW
+3.3VA
+3.3VD +3.3VA
ADCCLK
OEB
CON0
CON1
EXTREF
VINP
VINM
ADCCLK
OEB
CON0
CON1
EXTREF
VINM
D4
10
D5
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D6
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D7
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D8
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D9
5
D10
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D11
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D12
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D13
1
CLK
28
MODE
25
DVDD
27
DGND
26
AGND
20
AVDD
24
EXTLO
16
REFIO
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FSADJ
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COMP1
19
COMP2
23
IOUT1
22
IOUT2
21
SLEEP
15
D3
11
D2
12
D1
13
D0
14
U3
THS5671AIPW
LNK3
LNK2
LNK4
LNK5
R2
47K
R23
47K
R1
47K
R24
47K
+3.3VD
OEB
EXTREF
CON1
CON0
TP1
TP2
+
C28
10uF
C27
0.1uF
C25
0.1uF
C26
0.1uF
VRT
VRB
VRT
VRB
C62
470pF
C63
0.1uF
C64
470pF
C65
0.1uF
C66
470pF
C67
0.1uF
+3.3VD
_3.3VA
ADCOVRNG
ADCD00
ADCD01
ADCD02
ADCD03
ADCD04
ADCD05
ADCD06
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ADCD10
ADCD11
ADCD [00:11]
+3.3VA
+3.3VD
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ADCDB05
ADCDB06
ADCDB07
ADCDB08
ADCDB09
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ADCDB11
ADCDB[00:11]
DACCLK
C6
0.1uF
C15
0.1uF
+3.3VA
IOUT1
IOUT2
R10
2K
C16
0.01uF
C5
0.1uF
C19
10uF
C17
0.1uF
C18
0.1uF
+3.3VD
+3.3VA
CON1
OEB
EXTREF
IOUT1
IOUT2
+
VINP
DEFINITIONS OF SPECIFICATIONS AND TERMINOLOGY
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
Offset and Gain Error
THS1215
SLAS292A – MARCH 2001 – REVISED MARCH 2004
Figure 22. EVM Schematic
Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full scale.
The point used as zero occurs 1/2 LSB before the first code transition. The full-scale point is defined as level 1/2
LSB beyond the last code transition. The deviation is measured from the center of each particular code to the
true straight line between these two end-points.
An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value.
Therefore, this measure indicates how uniform the transfer function step sizes are. The ideal step size is defined
here as the step size for the device under test, i.e., (last transition level - first transition level)/(2n -2). Using this
definition for DNL separates the effects of gain and offset error. A minimum DNL better than -1 LSB ensures no
missing codes.
Offset error (in LSBs) is defined as the average offset for all inputs, and gain error is defined as the maximum
error (in LSBs) caused by the angular deviation from the offset corrected straight line.
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| THS1230CPWRG4 | 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28 |
| THS1230CDWRG4 | 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28 |
| THS1230IDWRG4 | 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| THS122 | 制造商:TOSHIBA 制造商全稱(chēng):Toshiba Semiconductor 功能描述:HIGH STABILITY MOTOR CONTROL. DIGITAL TACHOMETER. CRANK SHAFT POSITION SENSOR. |
| THS122(F) | 制造商:Toshiba 功能描述:Hall Effect Sensor 4-Pin 10-2A1A Bulk |
| THS123 | 制造商:TOSHIBA 制造商全稱(chēng):Toshiba Semiconductor 功能描述:HIGH STABILITY MOTOR CONTROL. DIGITAL TACHOMETER. CRANK SHAFT POSITION SENSOR. |
| THS1230 | 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:3.3-V, 12-BIT, 30 MSPS, LOW-POWER ANALOG-TO-DIGITAL CONVERTER WITH POWER DOWN |
| THS1230CDW | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Low Power High-Speed ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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