參數(shù)資料
型號: THS1206MDAREP
廠商: TEXAS INSTRUMENTS INC
元件分類: ADC
英文描述: 4-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO32
封裝: GREEN, PLASTIC, TSSOP-32
文件頁數(shù): 41/43頁
文件大?。?/td> 799K
代理商: THS1206MDAREP
THS1206EP
12BIT 6 MSPS, SIMULTANEOUS SAMPLING
ANALOGTODIGITAL CONVERTERS
SGLS126A JULY 2002 REVISED FEBRUARY 2003
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing specification of the single conversion mode
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tc
Clock cycle of the internal clock oscillator
159
167
175
ns
1 analog input
1.5
×tc
ns
t1
Pulse width, CONVST
2 analog inputs
2.5
×tc
t1
Pulse width, CONVST
3 analog inputs
3.5
×tc
4 analog inputs
4.5
×tc
tdA
Aperture time
1
ns
1 analog input
2
×tc
ns
t2
Time between consecutive start of single conversion
2 analog inputs
3
×tc
ns
t2
Time between consecutive start of single conversion
3 analog inputs
4
×tc
ns
4 analog inputs
5
×tc
ns
1 analog input,
TL = 1
6
×tc
ns
Delay time, DATA_AV becomes active for the trigger
2 analog inputs, TL = 2
7
×tc
ns
Delay time, DATA_AV becomes active for the trigger
level condition: TRIG0 = 0, TRIG1 = 0
3 analog inputs, TL = 3
8
×tc
ns
level condition: TRIG0 = 0, TRIG1 = 0
4 analog inputs, TL = 4
9
×tc
ns
1 analog input,
TL = 4
3
×t2 +6×tc
ns
td(DATA_AV)
Delay time, DATA_AV becomes active for the trigger
2 analog inputs, TL = 4
t2 +7×tc
ns
td(DATA_AV)
Delay time, DATA_AV becomes active for the trigger
level condition: TRIG0 = 1, TRIG1 = 0
3 analog inputs, TL = 6
t2 +8×tc
ns
level condition: TRIG0 = 1, TRIG1 = 0
4 analog inputs, TL = 8
t2 +9×tc
ns
1 analog input,
TL = 8
7
×t2 +6×tc
ns
Delay time, DATA_AV becomes active for the trigger
2 analog inputs, TL = 8
3
×t2 +7×tc
ns
Delay time, DATA_AV becomes active for the trigger
level condition: TRIG0 = 0, TRIG1 = 1
3 analog inputs, TL = 9
2
×t2 +8×tc
ns
level condition: TRIG0 = 0, TRIG1 = 1
4 analog inputs, TL = 12
2
×t2 +9×tc
ns
Delay time, DATA_AV becomes active for the trigger
1 analog input,
TL = 14
13
×t2 +6×tc
ns
td(DATA_AV)
Delay time, DATA_AV becomes active for the trigger
level condition: TRIG0 = 1, TRIG1 = 1
2 analog inputs, TL = 12
5
×t2 +7×tc
ns
td(DATA_AV)
level condition: TRIG0 = 1, TRIG1 = 1
3 analog inputs, TL = 12
3
×t2 +8×tc
ns
Timing parameters are ensured by design but are not tested.
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