參數(shù)資料
型號(hào): THS1206DA
廠商: Texas Instruments, Inc.
英文描述: 12-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
中文描述: 12 - MSPS的第6位,同步采樣模擬數(shù)字轉(zhuǎn)換器
文件頁(yè)數(shù): 8/41頁(yè)
文件大?。?/td> 564K
代理商: THS1206DA
THS1206
12-BIT 6 MSPS, SIMULTANEOUS SAMPLING
ANALOG-TO-DIGITAL CONVERTERS
SLAS217D – MAY 1999 – REVISED APRIL 2000
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing specifications
, AV
DD
= 5 V, BV
DD
= DV
DD
= 3.3 V, V
REF
= internal, C
L
< 30 pF
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ns
td(DATA_AV)
td(o)
Delay time
5
Delay time
5
ns
tpipe
Latency
5
CONV
CLK
timing specification of the single conversion mode
PARAMETER
TEST CONDITIONS
MIN
159
1.5
×
tc
TYP
167
MAX
UNIT
ns
tc
tw1
tdA
Clock cycle of the internal clock oscillator
175
Pulse width, CONVST
ns
Aperture time
1
ns
1 analog input
2
×
tc
3
×
tc
4
×
tc
5
×
tc
ns
t2
Time between consecutive start of single conversion
2 analog inputs
3 analog inputs
ns
4 analog inputs
1 analog input, TL = 1
6
×
tc
7
×
tc
8
×
tc
9
×
tc
ns
Delay time, DATA_AV becomes active for the trigger
level condition: TRIG0 = 0, TRIG1 = 0
2 analog inputs, TL = 2
3 analog inputs, TL = 3
ns
4 analog inputs, TL = 4
1 analog input, TL = 4
3
×
t2 +6
×
tc
t2 +7
×
tc
t2 +8
×
tc
t2 +9
×
tc
7
×
t2 +6
×
tc
3
×
t2 +7
×
tc
2
×
t2 +8
×
tc
2
×
t2 +9
×
tc
13
×
t2 +6
×
tc
5
×
t2 +7
×
tc
3
×
t2 +8
×
tc
ns
td(DATA AV)
td(DATA_AV)
Delay time, DATA_AV becomes active for the trigger
level condition: TRIG0 = 1, TRIG1 = 0
2 analog inputs, TL = 4
3 analog inputs, TL = 6
ns
4 analog inputs, TL = 8
1 analog input, TL = 8
ns
Delay time, DATA_AV becomes active for the trigger
level condition: TRIG0 = 0, TRIG1 = 1
2 analog inputs, TL = 8
3 analog inputs, TL = 9
ns
4 analog inputs, TL = 12
D l
Delay time, DATA_AV becomes active for the trigger
level condition: TRIG0 = 1 TRIG1 = 1
level condition: TRIG0 = 1, TRIG1 = 1
DATA AV b
th t i
1 analog input, TL = 14
ns
td(DATA_AV)
2 analog inputs, TL = 12
3 analog inputs, TL = 12
ns
Timing parameters are ensured by design but are not tested.
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