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參數資料
| 型號： | THS1060I |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 10-BIT 60 MSPS IF SAMPLING COMMUNICATIONS ANALOG-TO-DIGITAL CONVERTER |
| 中文描述： | 10位60 MSPS的IF采樣通訊模擬到數字轉換器 |
| 文件頁數： | 16/21頁 |
| 文件大?。?/td> | 353K |
| 代理商： | THS1060I |
THS1060
10-BIT 60 MSPS IF SAMPLING COMMUNICATIONS
ANALOG-TO-DIGITAL CONVERTER
SLAS212 – MARCH 2000
16
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
CLK+
VCM
THS1060
CLK–
Impedance Ratio = 1:4
3 V – 5 V p-p
0.01
μ
F
0.1
μ
F
T4-1H
Zo
4 Zo
0.1
μ
F
Figure 21. Coaxial Clock Source
The clock signals, CLK+ and CLK– should be well matched and must both be driven.
A transformer ensures minimal skew between the two complementary channels. However, skew levels of up
to 500 ps between CLK+ and CLK– can be tolerated with some performance degradation.
The clock input can also be driven differentially with a 5 V TTL signal by using an RF transformer to convert the
TTL signal to a differential signal. The TTL signal is ac coupled to the positive primary terminal with a high pass
circuit. The negative terminal of the transformer is connected to ground (see Figure 22). The transformer
secondary is connected to the CLK inputs.
CLK+
CLK–
VCM
THS1060
0.01
μ
F
0.1
μ
F
5 V TTL CLK
0.1
μ
F
Impedance Ratio = 1:4
T4 - 1H
Figure 22. TTL Clock Input
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