參數資料
型號: THS1040IPWRG4
廠商: TEXAS INSTRUMENTS INC
元件分類: ADC
英文描述: 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
封裝: GREEN, PLASTIC, TSSOP-28
文件頁數: 16/36頁
文件大?。?/td> 751K
代理商: THS1040IPWRG4
THS1040
SLAS290C OCTOBER 2001 REVISED OCTOBER 2004
23
www.ti.com
PRINCIPLES OF OPERATION
power management
In power-sensitive applications (such as battery-powered systems) where the THS1040 is not required to
convert continuously, power can be saved between conversion intervals by placing the THS1040 into
power-down mode. This is achieved by pulling the STBY pin high. In power-down mode, the device typically
consumes less than 0.1 mW of power.
If the internal VREF generator (A1) is not required, it can be powered down by tying pin REFSENSE to AVDD,
saving approximately 1.2 mA of supply current.
If the BIASREF function is not required when using internal references then tying MODE to AVDD/2 powers the
BIASREF buffer down, saving approximately 1.2 mA.
digital I/O
While the OE pin is held low, ADC conversion results are output at pins D0 (LSB) to D9 (MSB). The ADC input
over-range indicator is output at pin OVR. OVR is also disabled when OE is held high.
The only ADC output data format supported is unsigned binary (output codes 0 to 1023). Twos complement
output (output codes 512 to 511) can be obtained by using an external inverter to invert the D9 output.
相關PDF資料
PDF描述
THS1040IPWG4 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
THS1040CPWG4 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
THS1040CDWG4 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
THS1040CDWR 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
THS1040CPWRG4 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
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