參數(shù)資料
型號： THS1040IPW
廠商： TEXAS INSTRUMENTS INC
元件分類： ADC
英文描述： 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
封裝： GREEN, PLASTIC, TSSOP-28
文件頁數(shù)： 31/36頁
文件大?。?/td> 751K
代理商： THS1040IPW
THS1040
SLAS290C OCTOBER 2001 REVISED OCTOBER 2004
4
www.ti.com
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range: AVDD to AGND, DVDD to DGND
0.3 V to 4 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AGND to DGND
0.3 V to 0.3 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AVDD to DVDD
4 V to 4 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MODE input voltage range, MODE to AGND
0.3 V to AVDD + 0.3 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference voltage input range, REFT, REFB, to AGND
0.3 V to AVDD + 0.3 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog input voltage range, AIN to AGND
0.3 V to AVDD + 0.3 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference input voltage range, VREF to AGND
0.3 V to AVDD + 0.3 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference output voltage range, VREF to AGND
0.3 V to AVDD + 0.3 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock input voltage range, CLK to AGND
0.3 V to AVDD + 0.3 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital input voltage range, digital input to DGND
0.3 V to DVDD + 0.3 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital output voltage range, digital output to DGND
0.3 V to DVDD + 0.3 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating junction temperature range, TJ
0
°C to 150°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg
65
°C to 150°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 in) from case for 10 seconds
300
°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
over operating free-air temperature range TA, (unless otherwise noted)
PARAMETER
CONDITION
MIN
NOM
MAX
UNIT
Power Supply
Supply voltage
AVDD, DVDD
3
3.6
V
Analog and Reference Inputs
VREF input voltage
VI(VREF)
REFSENSE = AVDD
0.5
1
V
REFT input voltage
VI(REFT)
MODE = AGND
1.75
2
V
REFB input voltage
VI(REFB)
MODE = AGND
1
1.25
V
Reference input voltage
VI(REFT) VI(REFB) MODE = AGND
0.5
1
V
Reference common mode voltage
(VI(REFT)+VI(REFB))/2 MODE = AGND
(AVDD/2) 0.05
(AVDD/2) + 0.05
V
Analog input voltage differential (see Note 1)
VI(AIN)
REFSENSE = AGND
1
V
Analog input voltage differential (see Note 1)
VI(AIN)
REFSENSE = VREF
0.5
V
Analog input capacitance, CI
10
pF
Clock input (see Note 2)
0
AVDD
V
Digital Outputs
Maximum digital output load resistance
RL
100
k
Maximum digital output load capacitance
CL
10
pF
Digital Inputs
High-level input voltage, VIH
2.4
DVDD
V
Low-level input voltage, VIL
DGND
0.8
V
Clock frequency (see Note 3)
tc
f(CLK) = 5 MHz to 40 MHz 25
200
nS
Clock pulse duration
tw(CKL), tw(CKH)
f(CLK) = 40 MHz
11.25
12.5
13.75
nS
Operating free-air temperature, TA
THS1040C
0
70
°C
Operating free-air temperature, TA
THS1040I
40
85
°C
NOTE 1: VI(AIN) is AIN+ AIN range, based on VI(REFT) VI(REFB) =1V.Varies proportional to the VI(REFT) VI(REFB) value. Input common mode
voltage is recommended to be AVDD/2.
NOTE 2: The clock pin is referenced to AVSS and powered by AVDD.
NOTE 3: Clock frequency can be extended to this range without degradation of performance.
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