參數(shù)資料
型號(hào): THS1040CDW
廠商: TEXAS INSTRUMENTS INC
元件分類(lèi): ADC
英文描述: 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
封裝: GREEN, PLASTIC, SOIC-28
文件頁(yè)數(shù): 14/36頁(yè)
文件大?。?/td> 751K
代理商: THS1040CDW
THS1040
SLAS290C OCTOBER 2001 REVISED OCTOBER 2004
21
www.ti.com
PRINCIPLES OF OPERATION
onboard reference generator configuration (continued)
_
+
VBG
ADC
References
Buffer A2
MODE =
REFSENSE
AGND
VREF = External
AVDD
_
+
AVDD
2
or AVDD
Figure 28. Drive VREF Mode
operating configuration examples
Figure 29 shows a configuration using the internal ADC references for digitizing a single-ended signal with span
0 V to 2 V. Tying REFSENSE to ground gives 1 V at pin VREF. Tying MODE to AVDD/2 then sets the REFT and
REFB voltages via the internal reference generator for a 2-Vp-p ADC input range. The VREF pin provides the
1-V mid-scale bias voltage required at AIN. VREF should be well decoupled to AGND to prevent
sample-and-hold switching at AIN from corrupting the VREF voltage.
AIN+
AIN
VREF = 1 V
REFB
MODE
REFSENSE
AVDD/2
2 V
0 V
1 V
REFT
20
20
20 pF
10
F
0.1
F
0.1
F
10
F 0.1 F
20 pF
Figure 29. Operating Configuration: 2-V Single-Ended Input, Internal ADC References
相關(guān)PDF資料
PDF描述
THS1040IPW 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
THS1040CPWR 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
THS1040IPWRG4 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
THS1040IPWG4 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
THS1040CPWG4 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
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