參數(shù)資料
型號(hào): THS1031CPWG4
廠商: TEXAS INSTRUMENTS INC
元件分類: ADC
英文描述: 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
封裝: GREEN, PLASTIC, TSSOP-28
文件頁(yè)數(shù): 18/41頁(yè)
文件大?。?/td> 728K
代理商: THS1031CPWG4
THS1031
3-V TO 5.5-V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002
25
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
clamp operation (continued)
Line Sync
Black
Level
Video at AIN
CLAMP
Figure 29. Example Waveforms for Line-Clamping to a Video Input Black Level
clamp DAC output voltage range and limits
When using the internal clamp DAC in top/bottom or center span mode, the user must ensure that the desired
dc clamp level at AIN lies within the voltage range VREFBF to VREFTF. This is because the clamp DAC voltage
is constrained to lie within this range VREFBF to VREFTF. Specifically:
VDAC
+ V
REFBF ) (VREFTF * VREFBF)
(0.006
) 0.988
(DAC code) 1024)
DAC codes can range from 0 to 1023. Figure 30 graphically shows the clamp DAC output voltage versus the
DAC code.
VDAC
0
1023
VREFBF + 0.006(VREFTF–VREFBF)
VREFBF + 0.987(VREFTF–VREFBF)
DAC Code
VREFTF
VREFBF
Figure 30. Clamp DAC Output Voltage Versus DAC Register Code Value
If the desired dc level at AIN does not lie within the voltage range VREFTF to VREFBF, then either the CLAMPIN
pin can be used instead to provide a suitable reference voltage, or it may be possible to redesign the application
to move the AIN input range into the CLAMP DAC voltage range. This is achieved in both top/bottom and center
span modes by shifting both REFTS and REFBS up or down by the voltage through which the AIN input range
is to be moved.
(8)
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