參數(shù)資料
型號(hào)： THS1030IPWLE
廠(chǎng)商： TEXAS INSTRUMENTS INC
元件分類(lèi)： ADC
英文描述： 10-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
封裝： PLASTIC, TSSOP-28
文件頁(yè)數(shù)： 18/18頁(yè)
文件大?。?/td> 239K
代理商： THS1030IPWLE
THS1030
2.7 V ~ 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS243 – NOVEMBER 1999
9
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
Table 1. Mode Selection
MODES
ANALOG
INPUT
SPAN
MODE
PIN
REFSENSE
PIN
VREF
PIN
REFTS
PIN
REFBS
PIN
FIGURE
AIN
1 V
AVDD
Short together
AGND
2, 9
AIN
2 V
AVDD
AGND
Short together
AGND
3, 10
Top/bottom
AIN
1+Ra/Rb
AVDD
Mid Ra & Rb
Short together to Ra
AGND
4, 9, 10
AIN
External
VREF
AVDD
Short together
AGND
5, 9, 10
AIN
1 V
AVDD/2
Short together
2, 8
Center span
AIN
2 V
AVDD/2
AGND
NC
Short together to the
3, 8
Center span
AIN
1+Ra/Rb
AVDD/2
Mid Ra & Rb
Ra
g
common mode voltage
4, 8
AIN
VREF
AVDD/2
AVDD
External
5, 8
External
reference
AIN
2 V max
AGND
See Note 1
Voltage within supply
(REFTS–REBS) = 2 V max
6, 7
AIN is input 1
REFTS &
1 V
AVDD
Short together
Differential
input
REFBS are
shorted
2 V
AVDD
AGND
NC
Short together AVDD/2
11
together for
input 2
VREF
AVDD
External
NOTE 1: In external reference mode, VREF can be available for external use with CENTER SPAN set-up.
reference operations
VREF-pin reference
The voltage reference sources on the VREF pin are controlled by the REFSENSE pin as shown in NO TAG.
Table 2. VREF Reference Selection
REFSENSE
VREF
AGND
2 V
AVDD
The internal reference is disabled and an external reference should be connected to VREF pin.
Short to VREF
1 V
Connect to Ra/Rb
1+Ra/Rb
PRODUCT
PREVIEW
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