參數(shù)資料
型號: THS1030CDW
廠商: TEXAS INSTRUMENTS INC
元件分類: ADC
英文描述: 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
封裝: GREEN, PLASTIC, SOIC-28
文件頁數(shù): 10/37頁
文件大小: 727K
代理商: THS1030CDW
THS1030
3V TO 5.5V, 10BIT, 30 MSPS
CMOS ANALOGTODIGITAL CONVERTER
SLAS243E NOVEMBER 1999 REVISED DECEMBER 2003
18
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
top/bottom mode (MODE = AVDD)
Sample
and
Hold
1
1/2
ADC
Core
REFTF = AVDD + (REFTS REFBS)
AIN+
REFTS
REFBS
Internal
Reference
Buffer
REFBF = AVDD (REFTS + REFBS)
2
Figure 18. ADC Reference Generation Mode = AVDD
Connecting MODE to AVDD enables the internal reference buffer. Its inputs are internally switched to the REFTS
and REFBS pins and its outputs internally switched to pins REFTF and REFBF. The internal connections
(REFTS to REFTF) and (REFBS to REFBF) are broken.
The REFTS and REFBS voltages set the analog input span limits FS+ and FS respectively. Any voltages at
AIN greater than REFTS or less than REFBS will cause ADC over-range, which is signaled by OVR going high
when the conversion result is output.
Typically, REFSENSE is tied to AVDD to disable the ORG output to VREF (as in Figure 19), but the user can
choose to use the ORG output to VREF as either REFTS or REFBS.
AIN
REFTS
REFBS
REFTF
REFBF
REFSENSE
MODE
AVDD
+FS
FS
DC SOURCE = FS+
DC SOURCE = FS
0.1
F
10
F
0.1
F
0.1
F
Figure 19. Top/Bottom Reference Mode
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