參數(shù)資料
型號： THS10082CDA
廠商： Texas Instruments, Inc.
元件分類： ADC
英文描述： 10 bit TWO ANALOG INPUT, 8 MSPS SIMULTANEOUS SAMPLING ANALOG TO DIGITAL CONVERTER
中文描述： 10位2個模擬輸入，8 MSPS的同步采樣模數(shù)轉(zhuǎn)換器
文件頁數(shù)： 4/37頁
文件大小： 263K
代理商： THS10082CDA
SLAS254B
–
MAY 2002
–
REVISED NOVEMBER 2002
www.ti.com
4
ELECTRICAL CHARACTERISTICS
over recommended operating conditions, VREF = internal, fs = 8 MHz, fI = 2 MHz at
–
1 dB (unless otherwise noted)
AC SPECIFICATIONS, AVDD = 5 V, BVDD = DVDD = 3.3 V, CL < 30 pF
PARAMETER
TEST CONDITIONS
Differential mode
Single-ended mode(1)
Differential mode
Single-ended mode(1)
Differential mode
Single-ended mode
Differential mode
Single-ended mode(1)
Differential mode
Single-ended mode
MIN
56
55
59
TYP
59
58
61
60
–
67
–
63
9.5
9.35
65
64
MAX
UNIT
dB
dB
dB
dB
dB
dB
Bits
Bits
dB
dB
SINAD
Signal to noise ratio + distortion
Signal-to-noise ratio + distortion
SNR
Signal to noise ratio
Signal-to-noise ratio
THD
Total harmonic distortion
Total harmonic distortion
–
61
ENOB
Effective number of bits
9
SFDR
Spurious free dynamic range
61
Analog Input
Full-power bandwidth with a source impedance of 150
in
differential configuration.
Full-power bandwidth with a source impedance of 150
in
single-ended configuration.
Small-signal bandwidth with a source impedance of 150
in
differential configuration.
Small-signal bandwidth with a source impedance of 150
in
single-ended configuration.
(1)The SNR (ENOB) and SINAD is degraded typically by 2 dB in single-ended mode when the reading of data is asynchronous to the sampling
clock.
Full-scale sinewave,
–
3 dB
96
MHz
Full-scale sinewave,
–
3 dB
54
MHz
100-mVpp sinewave,
–
3 dB
96
MHz
100-mVpp sinewave,
–
3 dB
54
MHz
TIMING REQUIREMENTS
(1)
AVDD = DVDD = 5 V, BVDD = 3.3 V, VREF = internal, CL < 30 pF
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
td(DATA_AV)
td(o)
Delay time
5
ns
Delay time
5
ns
tpipe
Latency
5
CONV
CLK
(1)See Figure 27.
TIMING SPECIFICATION OF THE SINGLE CONVERSION MODE
(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tc
Clock cycle of the internal clock oscillator
117
125
133
ns
tw1
Pulse duration CONVST
Pulse duration, CONVST
One analog input
1.5
×
tc
2.5
×
tc
ns
Two analog inputs
td(A)
Aperture time
1
ns
t2
Delay time between consecutive start of
single conversion
One analog input
2
×
tc
3
×
tc
ns
Two analog inputs
One analog input, TL = 1
6.5
×
tc+15
7.5
×
tc+15
ns
Two analog inputs, TL = 2
One analog input, TL = 4
3
×
t2 +6.5
×
tc+15
t2 +7.5
×
tc+15
7
×
t2 +6.5
×
tc+15
3
×
t2 +7.5
×
tc+15
13
×
t2 +6.5
×
tc+15
13
×
t2 +6.5
×
tc+15
ns
td(DATA_AV)
Delay time, DATA_AV becomes active for the
trigger level condition: TRIG0 = 1, TRIG1 = 1
Two analog inputs, TL = 4
One analog input, TL = 8
ns
Two analog inputs, TL = 8
One analog input, TL = 14
ns
Two analog inputs, TL = 12
(1)See Figure 26.
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