參數(shù)資料
型號： THS1007IDAR
廠商： TEXAS INSTRUMENTS INC
元件分類： ADC
英文描述： 4-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO32
封裝： GREEN, PLASTIC, TSSOP-32
文件頁數(shù)： 18/34頁
文件大小： 364K
代理商： THS1007IDAR
THS1007
SLAS286B AUGUST 2000 REVISED DECEMBER 2010
www.ti.com
25
TIMING AND SIGNAL DESCRIPTION OF THE THS1007
The reading from the THS1007 and writing to the THS1007 is performed by using the chip select inputs (CS0,
CS1), the write input WR and the read input RD. The write input is configurable to a combined read/write input
(R/W). This is desired in cases where the connected processor consists of a combined read/write output signal
(R/W). The two chip select inputs can be used to interface easily to a processor.
Reading from the THS1007 takes place by an internal RDint signal, which is generated from the logical
combination of the external signals CS0, CS1 and RD (see Figure 33). This signal is then used to strobe the
words and to enable the output buffers. The last external signal (either CS0, CS1 or RD) to become valid makes
RDint active while the write input (WR) is inactive. The first of those external signals switching to its inactive state
deactivates RDint again.
Writing to the THS1007 takes place by an internal WRint signal, which is generated from the logical combination
of the external signals CS0, CS1 and WR. This signal strobes the control words into the control registers 0 and
1. The last external signal (either CS0, CS1 or WR) to become valid switches WRint active while the read input
(RD) is inactive. The first of those external signals going to its inactive state deactivates WRint again.
RD
WR
Control/Data
Registers
CS0
CS1
RD
WR
Data Bits
Figure 33. Logical Combination of CS0, CS1, RD, and WR
相關(guān)PDF資料
PDF描述
THS1007IDAG4 4-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO32
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