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參數(shù)資料
| 型號： | THS1007CDA |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 4-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO32 |
| 封裝： | GREEN, PLASTIC, TSSOP-32 |
| 文件頁數(shù)： | 9/34頁 |
| 文件大小： | 364K |
| 代理商： | THS1007CDA |
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THS1007
SLAS286B AUGUST 2000 REVISED DECEMBER 2010
www.ti.com
17
Sample N
Channel 1, 2
Sample N+1
Channel 1, 2
Sample N+2
Channel 1, 2
Sample N+3
Channel 1, 2
Data N1
Channel 2
Data N
Channel 1
Data N
Channel 2
Data N+1
Channel 1
Data N2
Channel 1
Data N2
Channel 2
Data N1
Channel 1
AIN
CONV_CLK
READ
READ is the logical combination from CS0, CS1 and RD
SYNC
td(A)
td(pipe)
tw(CONV_CLKH)
tw(CONV_CLKL)
tc
tsu(CONV_CLKL-READL)
tsu(READH-CONV_CLKL)
td(CONV_CLKL-SYNCL)
td(CONV_CLKL-SYNCH)
Figure 29. Conversion Timing in 2-Channel Operation
Figure 30 shows the conversion timing when three analog input channels are selected. The maximum
throughput rate per channel is 2 MSPS in this mode. The data flow in the bottom of the figure shows in which
order the converted data is available to the data bus. The SYNC signal is active low when the data of channel
one is available to the data bus. The data of channel one is followed by the data of channel two and channel
three before channel one is again available and the SYNC signal is active low.
Sample N
Channel 1, 2, 3
Sample N+1
Channel 1, 2, 3
Sample N+2
Channel 1, 2, 3
Data N1
Channel 3
Data N
Channel 1
Data N
Channel 2
Data N
Channel 3
Data N2
Channel 3
Data N1
Channel 1
Data N1
Channel 2
AIN
CONV_CLK
READ
READ is the logical combination from CS0, CS1 and RD
SYNC
td(A)
td(pipe)
tw(CONV_CLKH)
tw(CONV_CLKL)
tc
tsu(CONV_CLKL-READL)
tsu(READH-CONV_CLKL)
td(CONV_CLKL-SYNCL)
td(CONV_CLKL-SYNCH)
Figure 30. Conversion Timing in 3-Channel Operation
相關PDF資料 |
PDF描述 |
|---|---|
| THS1007CDAR | 4-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO32 |
| THS1007CDAG4 | 4-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO32 |
| THS1007IDA | 4-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO32 |
| THS1007IDAR | 4-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO32 |
| THS1007IDAG4 | 4-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO32 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| THS1007CDAG4 | 功能描述:模數(shù)轉換器 - ADC 10-Bit 6MSPS Simult Sampling Quad Ch RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| THS1007CDAR | 制造商:TI 制造商全稱:Texas Instruments 功能描述:10-BIT, 4 ANALOG INPUT, 6-MSPS, SIMULATANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER |
| THS1007IDA | 功能描述:模數(shù)轉換器 - ADC 10 BIT QUAD ADC w/o RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| THS1007IDAG4 | 功能描述:模數(shù)轉換器 - ADC 10-Bit 6MSPS Simult Sampling Quad Ch RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| THS1007IDAR | 制造商:TI 制造商全稱:Texas Instruments 功能描述:10-BIT, 4 ANALOG INPUT, 6-MSPS, SIMULATANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER |
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