參數(shù)資料
型號(hào)： THS10064IDA
廠商： TEXAS INSTRUMENTS INC
元件分類(lèi)： ADC
英文描述： 4-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO32
封裝： GREEN, PLASTIC, TSSOP-32
文件頁(yè)數(shù)： 7/42頁(yè)
文件大?。?/td> 527K
代理商： THS10064IDA
THS10064
SLAS255B – DECEMBER 1999 – REVISED DECEMBER 2002
www.ti.com
15
DETAILED DESCRIPTION
Reference Voltage
The THS10064 has a built-in reference, which provides the reference voltages for the ADC. VREFP is set to 3.5 V
and VREFM is set to 1.5 V. An external reference can also be used through two reference input pins, REFP and
REFM, if the reference source is programmed as external. The voltage levels applied to these pins establish the
upper and lower limits of the analog inputs to produce a full-scale and zero-scale reading respectively.
Analog Inputs
The THS10064 consists of 4 analog inputs, which are sampled simultaneously. These inputs can be selected
individually and configured as single-ended or differential inputs. The desired analog input channel can be
programmed.
Analog-to-Digital Converter
The THS10064 uses a 10-bit pipelined multistage architecture with 4 1-bit stages followed by 4 2-bit stages, which
achieves a high sample rate with low power consumption. The THS10064 distributes the conversion over several
smaller ADC sub-blocks, refining the conversion with progressively higher accuracy as the device passes the results
from stage to stage. This distributed conversion requires a small fraction of the number of comparators used in a
traditional flash ADC. A sample-and-hold amplifier (SHA) within each of the stages permits the first stage to operate
on a new input sample while the second through the eighth stages operate on the seven preceding samples.
Conversion Modes
The conversion can be performed in two different conversion modes. In the single conversion mode, the conversion
is initiated by an external signal (CONVST). An internal oscillator controls the conversion time. In the continuous
conversion mode, an external clock signal is applied to the clock input (CONV_CLK). A new conversion is started
with every falling edge of the applied clock signal.
Sampling Rate
The maximum possible conversion rate per channel is dependent on the selected analog input channels. Table 1
shows the maximum conversion rate in the continuous conversion mode for different combinations.
Table 1. Maximum Conversion Rate in Continuous Conversion Mode
CHANNEL CONFIGURATION
NUMBER OF
CHANNELS
MAXIMUM CONVERSION
RATE PER CHANNEL
1 single-ended channel
1
6 MSPS
2 single-ended channels
2
3 MSPS
3 single-ended channels
3
2 MSPS
4 single-ended channels
4
1.5 MSPS
1 differential channel
1
6 MSPS
2 differential channels
2
3 MSPS
1 single-ended and 1 differential channel
2
3 MSPS
2 single-ended and 1 differential channels
3
2 MSPS
The maximum conversion rate in the continuous conversion mode per channel, fc, is given by:
fc
+ 6MSPS
# channels
DATA_AV
In continuous conversion mode, the first DATA_AV signal is delayed by (7+TL) cycles of the CONV_CLK after a FIFO
reset. This is due to the latency of the pipeline architecture of the THS10064.
相關(guān)PDF資料
PDF描述
THS10064CDAR 4-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO32
THS10064IDAR 4-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO32
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