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參數(shù)資料
| 型號： | TH6503 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | USB Low-Speed Interface |
| 中文描述： | USB低速接口 |
| 文件頁數(shù)： | 3/24頁 |
| 文件大小： | 342K |
| 代理商： | TH6503 |
3
TH6503 USB Low-Speed Interface
Figure 3. TH6503 Block Diagram
Microcontroller
Interface
The data is transferred between the microcontroller and the USB bridge using the clock (SCK)
generated by the microcontroller asynchronous to the USB clock.
Data IN Transfer
(from the microcontroller to the TH6503)
Data IN transfer is initiated with rising SIN edge (IN
packet sync). Data is transferred via the SDI pin.
Initially the Adr/CntInRegister which indicates the
internal address in the TH6503 is written. Data is
subsequently transferred beginning with byte 0 to
Byte n LSB first. Bits IC3-IC0 in the Adr/CntInRegister
<3-0> contain the information on the number of
bytes to be transferred to the USB host if the target
of the data transfer was an IN FIFO.
A zero data transfer is identified with reset of IC3-
IC0 bits after writing the Adr/CntInRegister one
additional clock on SCK must be generated.
If a register is the target of the data IN transfer the
bits IC3-IC0 and TI have no meaning.
With falling SCK edge the microcontroller trans-
mit the bits to SDI and the bits are imported from
the bridge with increasing SCK edge. After each
transmission of 8 bits the respective IN FIFO value
is increased by 1. If the microcontroller writes
more data than indicated in the Adr/CntInRegister,
the oldest data are overwritten. After the final
falling edge of SCK first SDI and then SIN must be
reset to 0 to terminate the transfer. The associated
IN Done bit in the StatusRegister is reset automati-
cally to enable USB IN transfer.
TH6503/
Microcontroller
Cooperation
(continued)
USB
I/O
OCLK
V3.3
D+
D-
SIE
Serial
Interface
Engine
VBus
GND
Status Signals
Control Signals
Bus Interface
WAKE
R
Oscillator/
Divider
SCK
SIN
SDI
SDO
13
12
11
10
15
8
16
6
7
4
3
2
1
5
Power
Supply
3.3V
14
/ORST
1k5
10μ
Micro-
controller
Interface
V3.3
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