參數(shù)資料
型號(hào)： TFP6424PAP
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝： 10 X 10 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, THERMALLY ENHANCED, POWER, PLASTIC, TQFP-64
文件頁(yè)數(shù)： 39/65頁(yè)
文件大?。?/td> 813K
代理商： TFP6424PAP
TFP6422, TFP6424
PanelBus
DIGITAL TRANSMITTER/VIDEO ENCODER COMBO
SLDS118 – MARCH 2000
44
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PLL_Y
Subaddress = 4A
Default = 0xC9
7
6
5
4
3
2
1
0
PLL_Y[7:0]
Subaddress = 4B
Default = 0x35
7
6
5
4
3
2
1
0
PLL_Y[15:8]
Subaddress = 4C
Default = 0xD9
7
6
5
4
3
2
1
0
PLL_Y[23:16]
Subaddress = 4D
Default = 0x94
7
6
5
4
3
2
1
0
PLL_Y_SF
PLL_Y[29:24]
PLL_Y[29:0]
30-bit frequency control for the PLL that generates the video PORT CLKOUT.
PLL_Y_SF[1:0]
PLL_Y_SF scaling factor
Use the following equations to calculate PLL_Y:
For 1X output clock,
Y1 = X
× (FLEN+1) × 2^(PLL_X_SF–PLL_Y_SF)
Adjust PLL_F_SF such that 2^30 < Y1 <= 2^31
PLL_Y = Y1–2^30
A clock derived from the CLKOUT with the same frequency must be connected to CLKIN for the
correct operation.
For 2X output clock,
Y1 = X
× (FLEN+1) × 2^(PLL_X_SF–PLL_Y_SF–1)
Adjust PLL_F_SF such that 2^31 < Y1 <= 2^30
PLL_Y = Y1–2^30
A clock derived from the CLKOUT with half the frequency must be connected to CLKIN for the
correct operation.
Where:
FLEN +1 = Total number of lines per frame in the output video including active lines and vertical blanking
FLENS+1 = Total number of lines per frame in the input video including active lines and vertical blanking
The reset default values generate a 27 MHz clock on CLKOUT pin.
PRODUCT
PREVIEW
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