參數(shù)資料
型號(hào): TFP6422PAP
廠商: TEXAS INSTRUMENTS INC
元件分類: 消費(fèi)家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝: 10 X 10 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, THERMALLY ENHANCED, POWER, PLASTIC, TQFP-64
文件頁數(shù): 50/65頁
文件大小: 813K
代理商: TFP6422PAP
TFP6422, TFP6424
PanelBus
DIGITAL TRANSMITTER/VIDEO ENCODER COMBO
SLDS118 – MARCH 2000
54
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
L21ENA
L21ENB
Line21 ENCODING MODE
0(*)
Line21 encoding OFF
0
1
Enables encoding in 1st field (odd field)
1
0
Enables encoding in 2nd field (even field)
1
Enables encoding in both fields
HTRIGGER0
Subaddress = 6E
Default = 0x00
7
6
5
4
3
2
1
0
HTRIG[7:0]
LSB of horizontal trigger phase, which sets HSYNC. HTRIG is expressed in half-pixels or clk2x
periods.
HTRIGGER1
Subaddress = 6F
Default = 0x00
7
6
5
4
3
2
1
0
HTRIG[10:8]
HTRIG[11:8]
MSB of horizontal trigger phase, which sets HSYNC. HTRIG is expressed in half-pixels or clk2x
periods.
VTRIGGER0
Subaddress = 70
Default = 0x00
7
6
5
4
3
2
1
0
VTRIG[7:0]
Subaddress = 71
Default = 0xC0
7
6
5
4
3
2
1
0
PRESA
PRESB
SBLANK
VTRIG[9:8]
PRESA
Phase reset A. Used as shown in the register below.
PRESB
Phase reset B. Used as shown in the register below. Color subcarrier phase is reset to C_Phase
(subaddress 5A) upon reset.
SBLANK
Vertical blanking setting
0(*)
Vertical blanking is defined by the setting of FAL and LAL registers.
1
Vertical blanking is forced automatically during field synchronization and equalization.
VTRIG[9:0]
Vertical trigger reference for VSYNC. These bits specify the phase between VSYNC input and the
lines in a field. The VTRIG field is expressed in units of half-line.
PRESA
PRESB
PHASE RESET MODE
0
No resest
0
1
Reset every two lines
1
0
Reset every eight fields
1(*)
Reset every four fields
PRODUCT
PREVIEW
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