參數(shù)資料
型號(hào)： TFP510PAPG4
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝： 10 X 10 MM, 1 MM HEIGHT, 0.50 MM PITCH, GREEN, PLASTIC, HTQFP-64
文件頁(yè)數(shù)： 3/27頁(yè)
文件大小： 383K
代理商： TFP510PAPG4
TFP510
TI PanelBus DIGITAL TRANSMITTER
SLDS146B JANUARY 2002 REVISED DECEMBER 2002
11
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
universal graphics controller interface modes
Table 1 is a tabular representation of the different modes for the universal graphics controller interface. The
12-bit mode is selected when BSEL = 0 and the 24-bit mode when BSEL = 1. The 12-bit mode uses dual-edge
clocking and the 24-bit mode uses single-edge clocking. The EDGE input is used to control the latching edge
in 24-bit mode, or the primary latching edge in 12-bit mode. When EDGE = 1, the data input is latched on the
rising edge of the input clock; and when EDGE = 0, the data input is latched on the falling edge of the input clock.
A fully differential input clock is available only in the low-swing mode. Single-ended clocking is not
recommended in the low-swing mode as this decreases common-mode noise rejection.
Note that BSEL, DSEL, and EDGE are determined by register CTL_1_MODE when I2C is enabled (ISEL = 1)
and by input pins when I2C is disabled (ISEL = 0).
Table 1. Universal Graphics Controller Interface Options (Tabular Representation)
VREF
BSEL
EDGE
DSEL
BUS WIDTH
LATCH MODE
CLOCK EDGE
CLOCK MODE
0.55 V 0.9 V
0
12-bit
Dual-edge
Falling
Differential (see Notes 9 and 10)
0.55 V 0.9 V
0
1
12-bit
Dual-edge
Falling
Single-ended
0.55 V – 0.9V
0
1
0
12-bit
Dual-edge
Rising
Differential (see Notes 9 and 10)
0.55 V 0.9 V
0
1
12-bit
Dual-edge
Rising
Single-ended
0.55 V – 0.9 V
1
0
24-bit
Single-edge
Falling
Single-ended
0.55 V – 0.9 V
1
0
1
24-bit
Single-edge
Falling
Differential (see Notes 9 and 11)
0.55 V – 0.9 V
1
0
24-bit
Single-edge
Rising
Single-ended
0.55 V – 0.9 V
1
24-bit
Single-edge
Rising
Differential (see Notes 9 and 11)
DVDD
0
X
12-bit
Dual-edge
Falling
Single-ended (see Note 12)
DVDD
0
1
X
12-bit
Dual-edge
Rising
Single-ended (see Note 12)
DVDD
1
0
X
24-bit
Single-edge
Falling
Single-ended (see Note 12)
DVDD
1
X
24-bit
Single-edge
Rising
Single-ended (see Note 12)
NOTES:
9. The differential clock input mode is only available in the low signal swing mode (i.e., VREF ≤ 0.9 V).
10. The TFP510 does not support a 12-bit dual-clock, single-edge input clocking mode.
11. The TFP510 does not support a 24-bit single-clock, dual-edge input clocking mode.
12. In the high-swing mode (VREF = DVDD), DSEL is a don’t care; therefore, the device is always in the single-ended latch mode.
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