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參數(shù)資料
| 型號(hào)： | TFF11080HN |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Low phase noise LO generator |
| 封裝： | TFF11080HN/N1<SOT616-1 (HVQFN24)|<<http://www.nxp.com/packages/SOT616-1.html<1<Always Pb-free,; |
| 文件頁數(shù)： | 5/9頁 |
| 文件大?。?/td> | 2830K |
| 代理商： | TFF11080HN |
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High-speed data converters
Our highly competitive high-speed ADCs and DACs feature three different data interfaces, including the industry’s first
implementation of JEDEC JESD204A (2008). This new standardized serial interface dramatically reduces the number of interconnect
signals between data converters and logic devices. It also solves one of the major base station (and other I/Q modulation
communications systems) design challenges by synchronously bonding multiple data channels or lanes.
ADCs
Our single- and dual-channel ADC portfolio offers more than 80 different
ADCs with resolutions from 8 to 16 bits, input samples rates from 20 to
125 Msps, optional input buffer and low-voltage CMOS, LVDS/DDR and
JEDEC JESD204A digital outputs.
The ADC1413D is a dual-channel 14-bit Analog-to-Digital Converter (ADC) optimized for high dynamic performance and low
power at sample rates up to 125 Msps. A pipelined architecture and output error correction ensure the ADC1413D is accurate
enough to guarantee zero missing codes over the entire operating range. Supplied from a 3 V source for analog and a 1.8 V
source for the output driver, it embeds two serial outputs. Each lane is differential and complies with the JESD204A standard. An
integrated Serial Peripheral Interface (SPI) allows the user to easily configure the ADCs. A set of IC configurations is also available
via the binary level control pins, which are used at power-up. The device also includes a programmable full-scale SPI to allow
a flexible input voltage range of 1 to 2 V (peak-to-peak). Excellent dynamic performance (SNR=71.4 Db, SFDR=87 dBc typ) is
maintained from the baseband to input frequencies of 170 MHz or more, making the ADC1413D ideal for use in communications,
imaging, and medical applications.
DACs
Our dual-channel DACs portfolio offers DACs with resolutions of 10, 12
or 14 bits, output samples rates from 125 to 750 Msps, and low-voltage
CMOS, LVDS/DDR or JEDEC JESD204A digital inputs.
The DAC1408D750 is a high-speed 14-bit dual channel Digital-to-Analog Converter (DAC) with selectable, 2x, 4x or 8x
interpolating filters optimized for multi-carrier WCDMA transmitters up to 750 Msps. Thanks to its digital on-chip modulation,
the DAC1408D750 allows the complex pattern provided through the lanes to be converted up from baseband to IF. The mixing
frequency is adjusted via a Serial Peripheral Interface (SPI) with a 32-bit Numerically Controlled Oscillator (NCO) and the phase is
controlled by a 16-bit register. The serial input digital interface (maximum data rate of 3.125 Gbps) is compliant with the JEDEC
JESD204A standard. NXP’s implementation of Multiple Device Synchronization (MDS) enables the data streams of several DACs
to be sample synchronized and phase coherent.
CVG – The industry’s first implementation of the JESD204A serial interface
CGV (Convertisseur Grande Vitesse), NXP’s 100% JEDEC JESD204A-compliant interface that NXP enhanced for even greater
ease-of-use and improved performance:
`
Enhanced rate (up to 4.0 Gbps) a 28% increase over the JEDEC standard 3.125 Gbps
`
Enhanced reach (up to 100 cm) a 400% increase over the JEDEC standard 20 cm
`
Enhanced features (multiple DAC synchronization) enables up to sixteen DAC data streams to be
sample-synchronized and phase-coherent
`
Comprehensive interoperability with SERDES-based FPGAs eliminates the risk and cost associated
with project schedules
`
NXP CGV ADCs and DACs support FPGAs from Altera, Lattice and Xilinx giving you plug-and-play interop!
ADC1413D125 Demoboard
Features
QUBiC4+
QUBiC4X
QUBiC4X
Release for production
2004
2006
2008
CMOS/Bipolar
CMOS 0.25
μ
m, Bipolar 0.4
μ
m,
Double poly, Deep trench, Si
CMOS 0.25
μ
m, Bipolar LV 0.4
μ
m,
Double poly, Deep trench, SiGe:C
CMOS 0.25
μ
m, Bipolar LV 0.3
μ
m,
Double poly, Deep trench, SiGe:C
LV NPN f
T
/F
max
(GHz)
HV NPN f
T
/F
max
(GHz)
NPN BVce0: HV/LV **
37/90 (Si)
137/180 (SiGe:C)
180/200 (SiGe:C)
28/70 (Si)
60/120 (SiGe:C)
tbd (SiGe:C)
5.9 / 3.8 V
3.2 / 2.0 V
2.5 / 1.4 V
V-PNP f
T
/ BVcb0 (GHz / V)
CMOS Voltage /
Dual Gate
7 / >9
planned
planned
2.5 / 3.3 V
2.5 V
2.5 V
Noise figure NPN (dB)
2 GHz: 1.1
10 GHz: 0.8
10 GHz: 0.5
RFCMOS f
T
(GHz)
Isolation (60 dB @ 10 GHz)
NMOS 58, PMOS 19
NMOS 58, PMOS 19
NMOS 58, PMOS 19
STI and DTI
STI and DTI
STI and DTI
Interconnection
(AlCu with CMP W Plugs)
5 LM, 3 μm top Metal
5 LM, 3 μm top Metal
2 μm M4
5 LM, 3 μm top Metal
Capacitors
NW, DN, Poly-Poly
5 fF/
μ
m
2
MIM
NW, DN, Poly-Poly
5 fF/
μ
m
2
MIM
NW, DN, Poly-Poly
5 fF/
μ
m
2
MIM
Resistors (/sq)
Poly (64/220/330/2K), Active (12, 57),
High Precision SiCr (270)
Poly (64/220/330/2K), Active (12, 57),
High Precision SiCr (270)
Poly (64/220/330/2K), Active (12, 57),
High Precision SiCr (270)
Varicaps (single-ended &
differential)
2x single ended, Q > 40
3x differential, Q 30-50
2x single ended, Q > 40
3x differential, Q 30-50
2x single ended, Q > 40
3x differential, Q 30-50
Inductors (1.5 nH @
2 GHz) - scalable
Q > 21, Thick Metal, Deep trench isolation,
High R substrate
Q > 21, Thick Metal, Deep trench isolation,
High R substrate
Q > 21, Thick Metal, Deep trench isolation,
High R substrate
Other devices
LPNP, Isolated NMOS
Isolated-NMOS
LPNP, Isolated-NMOS
Mask count
31 / 32 (MIM) / 33 (DG)
35 (MIM)
35 (MIM)
QUBiC4+
BiCMOS
f /f
max
= 37/90 GHz
+DG
+TFR
+VPNP
+HVNPN
-4ML
SiGe:C
f / f
max
= 137/180 GHz
QUBiC4X
SiGe:C
f
T
/
f
max
= 180/200 GHz
QUBiC4Xi
QUBiC4+
`
Baseline, 0.25 μm CMOS, single poly, 5 metal
`
Digital gate density 26k gates/mm
2
`
f
T
/f
MAX
= 37/90 GHz
`
+TFR – Thin Film Resistor
`
+DG – Dual Gate Oxide MOS
`
+HVNPN – High Voltage NPN
`
+VPNP – Vertical PNP (high V
early
)
`
-4ML – high density 5 fF/μm
2
MIM capacitor
`
Wide range of active and high quality passive devices
`
Optimized for up to 5 GHz applications
QUBiC4X
`
SiGe:C process
`
f
T
/f
MAX
= 137/180 GHz
`
Optimized for up to 30 GHz applications
`
Transformers
QUBiC4Xi
`
SiGe:C process
`
Improves f
T
/f
max
up to 180/200 GHz
`
Optimized for ultra-low noise for microwave above 30 GHz
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