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參數(shù)資料
| 型號： | TFDU6102 |
| 廠商： | Vishay Intertechnology,Inc. |
| 英文描述： | Fast IrDA with long Link Distance of > 1Meter; |
| 中文描述： | 快速IrDA，長鏈路距離>1米 |
| 文件頁數(shù)： | 9/16頁 |
| 文件大?。?/td> | 420K |
| 代理商： | TFDU6102 |
VISHAY
TFDU6102
Vishay Semiconductors
Document Number 82550
Rev. 1.5, 24-Jun-04
www.vishay.com
9
I/O and Software
In the description, already different I/Os are men-
tioned. Different combinations are tested and the
function verified with the special drivers available
from the I/O suppliers. In special cases refer to the I/
O manual, the Vishay application notes, or contact
directly Vishay Sales, Marketing or Application.
Mode Switching
The TFDU6102 is in the SIR mode after power on as
a default mode, therefore the FIR data transfer rate
has to be set by a programming sequence using the
Txd and SD inputs as described below or selected by
setting the Mode Pin. The Mode Pin can be used to
statically set the mode (Mode Pin: LOW: SIR, HIGH:
0.576 Mbit/s to 4.0 Mbit/s). If not used or in standby
mode, the mode input should float or should not be
loaded with more than 50 pF. The low frequency
mode covers speeds up to 115.2 kbit/s. Signals with
higher data rates should be detected in the high fre-
quency mode. Lower frequency data can also be
received in the high frequency mode but with reduced
sensitivity.
To switch the transceivers from low frequency mode
to the high frequency mode and vice versa, the pro-
gramming sequences described below are required.
Setting to the High Bandwidth Mode
(0.576 Mbit/s to 4.0 Mbit/s)
1. Set SD input to logic "HIGH".
2. Set Txd input to logic "HIGH". Wait t
s
≥
200 ns.
3. Set SD to logic "LOW" (this negative edge latches
state of Txd, which determines speed setting).
4. After waiting t
h
≥
200 ns Txd can be set to logic
"LOW". The hold time of Txd is limited by the maxi-
mum allowed pulse length.
After that Txd is enabled as normal Txd input and the
transceiver is set for the high bandwidth (576 kbit/s to
4 Mbit/s) mode.
Setting to the Lower Bandwidth Mode
(2.4 kbit/s to 115.2 kbit/s)
1. Set SD input to logic "HIGH".
2. Set Txd input to logic "LOW". Wait t
s
≥
200 ns.
3. Set SD to logic "LOW" (this negative edge latches
state of Txd, which determines speed setting).
4. Txd must be held for t
h
≥
200 ns.
After that Txd is enabled as normal Txd input and the
transceiver is set for the lower bandwidth (9.6 kbit/s to
115.2 kbit/s) mode.
Table 2.
Truth table
Figure 2. Mode Switching Timing Diagram
Txd
SD/Mode
t
s
t
h
50%
High : FIR
Low : SIR
50%
50%
14873
Inputs
Outputs
SD
Txd
Optical input Irradiance mW/m
2
x
Rxd
Transmitter
high
x
weakly pulled
(500 k
) to V
CC1
low (active)
0
low
high
x
I
e
0
0
0
high > 80
μ
s
low
low
x
high
high
< 4
> Min. Detection Threshold Irradiance
< Max. Detection Threshold Irradiance
> Max. Detection Threshold Irradiance
low (active)
low
x
0
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| TFDU6102_05 | 制造商:VISHAY 制造商全稱:Vishay Siliconix 功能描述:Fast Infrared Transceiver Module (FIR, 4 Mbit/s) for 2.7 V to 5.5 V Operation |
| TFDU6102E | 制造商:VISHAY 制造商全稱:Vishay Siliconix 功能描述:Fast Infrared Transceiver Module Family (FIR, 4 Mbit/s) for 2.6 V to 5.5 V Operation |
| TFDU6102E-TR3 | 制造商:VISHAY 制造商全稱:Vishay Siliconix 功能描述:Fast Infrared Transceiver Module Family (FIR, 4 Mbit/s) for 2.6 V to 5.5 V Operation |
| TFDU6102E-TT3 | 制造商:VISHAY 制造商全稱:Vishay Siliconix 功能描述:Fast Infrared Transceiver Module Family (FIR, 4 Mbit/s) for 2.6 V to 5.5 V Operation |
| TFDU6102-TR3 | 功能描述:紅外收發(fā)器 FIR 4 Mbits/s RoHS:否 制造商:Vishay Semiconductors 波長:900 nm 連續(xù)數(shù)據(jù)傳輸:115.2 Kbit/s 傳輸距離:1 m 輻射強(qiáng)度:60 mW/sr 半強(qiáng)度角度:44 deg 脈沖寬度:2 us 最大上升時間:100 ns 最大下降時間:100 ns LED 電源電壓:- 0.5 V to 6 V 最大正向電流:80 mA 工作電壓:2.4 V to 5.5 V 最大工作溫度:+ 85 C 最小工作溫度:- 25 C 尺寸:6 mm x 3.1 mm x 1.9 mm 封裝 / 箱體: 封裝:Reel |
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