參數(shù)資料
型號(hào): TEA6843HL/V1,518
廠商: NXP SEMICONDUCTORS
元件分類: 接收器
英文描述: AM/FM, AUDIO SINGLE CHIP RECEIVER, PQFP80
封裝: 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-315-1, LQFP-80
文件頁數(shù): 29/62頁
文件大?。?/td> 363K
代理商: TEA6843HL/V1,518
2003 Dec 19
35
Philips Semiconductors
Product specication
New In Car Entertainment (NICE)
extended car radio
TEA6843HL
Table 2
Read mode
Notes
1. S = START condition.
2. A = acknowledge.
Table 3
IC address byte
Notes
1. Defined by address pin FREF:
a) 1 = 1st IC address
b) 0 = 2nd IC address.
2. Read or write mode:
a) 0 = write operation to TEA6843HL
b) 1 = read operation from TEA6843HL.
12.2.2
WRITE MODE: DATA BYTE 1
Table 4
Format of data byte 1
Table 5
Description of data byte 1 bits
12.2.3
WRITE MODE: DATA BYTE 2
Table 6
Format of data byte 2
Table 7
Description of data byte 2 bits
address (read)
data byte 1
IC ADDRESS
MODE
110000
R/W(2)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
AF
PLL14
PLL13
PLL12
PLL11
PLL10
PLL9
PLL8
BIT
SYMBOL
DESCRIPTION
7AF
Alternative frequency. If AF = 0, then normal operation. If AF = 1, then AF (RDS)
update mode.
6 to 0
PLL[14:8]
Setting of programmable counter of synthesizer PLL. Upper byte of PLL divider
word.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
PLL7
PLL6
PLL5
PLL4
PLL3
PLL2
PLL1
PLL0
BIT
SYMBOL
DESCRIPTION
7 to 0
PLL[7:0]
Setting of programmable counter of synthesizer PLL. Lower byte of PLL divider
word.
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