參數(shù)資料
型號: TEA5766UK/N1,023
廠商: NXP SEMICONDUCTORS
元件分類: 接收器
英文描述: FM, AUDIO SINGLE CHIP RECEIVER, PBGA25
封裝: 3.30 X 3.25 MM, 0.60 MM HEIGHT, WLCSP-25
文件頁數(shù): 58/59頁
文件大?。?/td> 273K
代理商: TEA5766UK/N1,023
TEA5766UK_1
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 22 March 2007
8 of 59
NXP Semiconductors
TEA5766UK
Stereo FM radio + RDS
7.12.2 Hard mute
With the MU bit of the TNCTRL register byte 2 (see Table 16), the audio outputs VAFL and
VAFR can be hard-muted; this means they are put in high-impedance state. The same
can be done by setting the bits Left Hard Mute (LHM) or Right Hard Mute (RHM) in
register TESTREG (see Table 19), which mute only one output at a time (or both when
both set). When one output is muted the stereo decoder switches to mono. When he
TEA5766UK is in Standby mode the audio outputs are in high-impedance state (see
7.12.3 Audio Frequency Mute (AFM)
With the AFM bit of the TNCTRL register byte 1, the audio signal can be muted. The audio
pins maintain their functional impedance and DC-biasing level while the audio signal is
muted. The audio frequency mute is automatically activated during preset as well as
search tuning modes as shown in the owchart of Figure 4. The audio frequency mute
can be disabled in software test mode when bit TM = 1 and bit AFMDIS = 1.
7.12.4 Specication of mute modes
7.13 MPX decoder
The stereo decoder PLL is adjustment free. The stereo decoder can be switched to mono
via the control interface.
7.14 Signal depending mono/stereo blend (stereo noise cancellation)
With decreasing RF input level the MPX decoder blends from stereo to mono to limit the
output noise. The continuous mono-to-stereo blend can also be programmed via the
control interface to an RF level depending switched mono to stereo transition. Stereo
noise cancellation can be switched on or off via the control interface using bit SNC in
register TNCTRL (see Table 16). When stereo noise cancellation is switched off, the radio
switches from mono to stereo instead of blending. The RF input voltage where blending
starts can be switched with bit SNCLEV in register TESTREG (see Table 19).
7.15 Software programmable port
One software programmable port SWPORT (CMOS output) is available and can be
controlled via the control interface. With bit SWPM = 1 the software port (pin SWPORT)
functions as the output for the FRRFLAG and with bit SWPM = 0 the software port output
follows bit SWP. Bits SWP and SWPM are in register TNCTRL (seeTable 16). In software
Table 4.
Specication of mute modes
Type
Description
VAFL
VAFR
Impedance
Mode
Impedance
Mode
AFM
audio frequency
mute
350
muted
350
muted
RHM
right hard mute
350
mono audio
> 500 k
muted
LHM
left hard mute
> 500 k
muted
350
mono audio
MU
hard mute
> 500 k
muted
> 500 k
muted
Standby
standby
> 1 M
-> 1 M
-
SMUTE
soft mute
RF sensitive audio level; has no inuence on mute pin or impedance
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