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參數(shù)資料
| 型號： | TEA5760UK/N1/S21,0 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA25 |
| 封裝： | 3 X 2.80 MM, 0.60 MM HEIGHT, WLCSP-25 |
| 文件頁數(shù)： | 9/37頁 |
| 文件大?。?/td> | 209K |
| 代理商： | TEA5760UK/N1/S21,0 |
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TEA5760UK_1
NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 14 December 2006
16 of 36
NXP Semiconductors
TEA5760UK
Single chip FM stereo radio
8.
I2C-bus interface
The I2C-bus interface is based on
The I2C-bus specication, version 2.1 January 2000,
expanded by the following denitions.
8.1 Write and read mode
8.2 Data transfer
Structure of the I2C-bus:
Slave transceiver
Subaddresses not used
Remark: The I2C-bus operates at a maximum clock rate of 400 kHz. It is not allowed to
connect the TEA5760UK to an I2C-bus operating at a higher clock rate.
Data transfer to the TEA5760UK:
Bit 7 of each byte is considered the MSB and has to be transferred as the rst bit of
the byte.
The LSB indicates the write or read action.
Fig 7.
Write mode
001aac341
chip address
R/W
byte0W
byte6W
0010 0000
0
xxxx xxxx
.....
S
BYTE 1
A
BYTE 2
A
BYTE n
BYTE 8
NAK
P
Fig 8.
Read mode
001aac342
chip address
R/W
byte0R
byte15R
0010 0000
1
xxxx xxxx
.....
S
BYTE 1
A
BYTE 2
A
BYTE n
BYTE 17
A
P
Table 7.
I2C-bus transfer description
Code
Description
S
START condition
Byte 1
I2C-bus chip address (7 bits)
R/W = 0 for write action and R/W = 1 for read action
A
acknowledge (SDA = LOW)
Byte 2, etc.
data byte (8 bits)
NAK
non acknowledge (SDA = HIGH)
P
STOP condition
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