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參數(shù)資料
| 型號： | TEA5760UK/N1,118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA25 |
| 封裝： | 3 X 2.80 MM, 0.60 MM HEIGHT, WLCSP-25 |
| 文件頁數(shù)： | 8/37頁 |
| 文件大?。?/td> | 209K |
| 代理商： | TEA5760UK/N1,118 |
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TEA5760UK_1
NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 14 December 2006
15 of 36
NXP Semiconductors
TEA5760UK
Single chip FM stereo radio
7.1.4.3
RSSI threshold: LEVFLAG
The level voltage reects the eld strength received by the antenna. The level voltage is
analog-to-digital converted with 4 bits and output via the control interface. This 4-bit level
value can be compared to a threshold level set by the SSL bits (see Table 14). The level
ADC (which converts the analog value to digital) is triggered by a search or preset cycle.
During a tuning step, which can be a search or a preset it is triggered by these algorithms
and compares the level with the threshold set by the SSL bits. The LEVFLAG bit is set if
the RSSI level drops below the threshold level set by the SSL bits (see Table 14), the HW
interrupt is only generated if the corresponding mask bit is set.
7.1.4.4
Frequency ready ag: FRRFLAG
The frequency ready ag bit FRRFLAG is set to logic 1 when the automatic tuning has
nished a search or preset. The description of this bit is given in Table 9. This bit is
cleared by a read of the ag register.
7.1.4.5
Band limit: BLFLAG
The band limit bit BLFLAG is set to logic 1 when the automatic tuning has detected the
end of the tuning band. This bit is described in Table 9. This bit is cleared by a read of the
ag register.
7.2 Interrupt line
The interrupt line driver is a MOS transistor with a nominal sink current of 900
A. It is
pulled HIGH by an 18 k
resistor connected to pin VREFDIG. The interrupt line can be
connected to one other similar device with an interrupt output and an 18 k
pull-up
resistor, providing a wired-OR function. This allows any of the drivers to pull the interrupt
line LOW by sinking the current (see Section 11). When a ag is set and not masked it
generates an interrupt.
(1) When Flag is set next interrupts are blocked until Read/Write INTMSK.
(2) Read INTMSK clears Flag, INTMSK and INTX.
(3) Write INTMSK enables INTX.
Fig 6.
Interrupt line behavior
001aab489
10 ms
VCCA
flag(1)
INTX
read INTMSK(2)
write
INTMSK(3)
10 ms
<10 ms
read clears INTX
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