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參數(shù)資料
| 型號(hào)： | TEA1795T/N1 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | SWITCHING CONTROLLER, 500 kHz SWITCHING FREQ-MAX, PDSO8 |
| 封裝： | 3.90 MM, PLASTIC, MS-012, SOT96-1, SOP-8 |
| 文件頁數(shù)： | 10/14頁 |
| 文件大?。?/td> | 134K |
| 代理商： | TEA1795T/N1 |
TEA1795T
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 1 — 4 November 2010
5 of 14
NXP Semiconductors
TEA1795T
GreenChip synchronous rectifier controller
The zero current is detected by sensing a Vdeact(drv) (12 mV typical) difference between
the drain sense pins and the source sense pins (see Figure 4). A synchronous
rectification off-timer (toff(sr)(min), 400 ns typical) is started and the next switching cycle can
only be started when the synchronous rectification off-timer has finished.
7.5 Gate driver (GDA and GDB pins)
The gate driver circuit to the gate of the external SR MOSFET has a source capability of
typically 400 mA and a sink capability of typically 2.7 A. This allows fast turn-on and
turn-off of the external SR MOSFET for efficient operation. The source stage is coupled to
the timer (see Figure 1). When the timer has finished, the source capability is reduced to a
small current (4 mA typical) capable of keeping the driver output voltage at its level.
The output voltage of the driver is limited to 10 V (typical). This high output voltage drives
all MOSFET brands to the minimum on-state resistance.
During start-up conditions (VCC <Vstartup) and UVLO the driver output voltage is actively
pulled low.
7.6 Source sense (SSA and SSB pins)
The IC is equipped with additional source sense pins (SSA and SSB). These pins are
used for the measurement of the drain-to-source voltage of the external SR MOSFET.
This drain-to-source voltage determines the timing of the gate driver. The source sense
input should be connected as close as possible to the source pin of the external
SR MOSFET to minimize timing errors, caused by voltage difference on PCB tracks, due
to parasitic inductance in combination with large dI/dt values.
Fig 4.
Synchronous rectification signals
001aal798
tact(sr)(min)
toff(sr)(min)
secondary
current
0 A
0 V
Vdeact(drv)
Vreg(drv)
Vact(drv)
0 V
t
drain sense-
source sense
voltage
gate driver
blanking
windows
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