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參數(shù)資料
| 型號： | TEA0675T-T |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 噪聲抑制 |
| 英文描述： | B Type, DOLBY NOISE REDUCTION IC, PDSO24 |
| 封裝： | 7.50 MM, PLASTIC, MS-013AD, SOT-137-1, SOP-24 |
| 文件頁數(shù)： | 6/32頁 |
| 文件大?。?/td> | 225K |
| 代理商： | TEA0675T-T |
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1996 Jun 07
14
Philips Semiconductors
Preliminary specication
Dual Dolby* B-type noise reduction circuit
for playback applications
TEA0675
Description of the principle timing diagram for AMS-latch mode with initial input signal (see Fig.8)
Fig.8 AMS-latch mode with initial input signal.
handbook, full pagewidth
MED628
output signal
to power FET
4.5 V
VAMSEQ
time threshold
upper threshold
(hysteresis)
Vt
VREF
level threshold
Vl
Vin
tr: rise time
td: delay time
tb: burst time
tp: pause time
tf: fall time
Vl: voltage at
level detector
input
pin 3 (CONTRA)
Vt: voltage at
time detector
input
pin 22 (CONTRB)
t
internal
latch status
L
H
t
AMS on
td
tf
tb<tr
tp<td
t0 t1
t5 t6
t7 t8 t9 t10
t11 t12
t13 t14
t15
This is similar to the description in Section “Description of
the principle timing diagram for AMS-scan mode with initial
input signal (see Fig.6)”. It only differs in its rise time tr and
a release of its internal latch when voltage Vt passes the
upper threshold between t0 and t1. Now the initial
procedure is completed.
The following behaviour does not differ from the
description in Section “Description of the principle timing
diagram for AMS-latch mode without initial input signal
(see Fig.7)”.
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